Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-01-07
2004-05-11
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189050, C365S189120
Reexamination Certificate
active
06735131
ABSTRACT:
BACKGROUND
This invention relates to weak current generation.
Weak current generation plays a part, for example, in a weak write test mode (WWTM) for static random access memories (SRAMs). The WWTM uses test circuitry that attempts to overwrite data stored in cells of an SRAM. Cells in which the data is successfully overwritten are considered to be defective. (See
Weak Write Test mode: A SRAM Cell Stability Design for Test Technique
, IEEE Intentional Test Conference, July 1997, incorporated by reference).
As shown in
FIG. 1
, an SRAM column, for example, can be driven by an SRAM column write driver
10
. Driver
10
uses conventional inverters
16
,
18
(comprised of devices
20
,
22
,
26
,
28
) to invert, respectively, input signal din
24
to produce bit #
12
and input signal din #
30
to produce bit
14
.
In normal operation, a weak write control signal weak #
32
is held high (logic 1), keeping p-device
34
on and (through inverter
38
) p-device
36
off. n-device
40
is also kept on.
Driver
10
is placed into WWTM mode by driving weak #
32
low, which switches device
34
on and device
36
off. Device
40
also turns off. Diode-connected transistor
44
then supplies a weak write current onto either bit
12
or bit #
14
, depending on which of the inputs din or din # is on. By a “weak” current we mean a current in the range of tens of nano-amperes to a few micro amperes.
The diode-connected transistor
44
is carefully sized using SPICE simulations, but mismatches can occur between the simulation and the related physical device (e.g., a fabricated chip).
Multiple diodes can be stacked to obtain different current values.
REFERENCES:
patent: 5559745 (1996-09-01), Banik et al.
patent: 5828827 (1998-10-01), Mateja et al.
patent: 5912550 (1999-06-01), Sharpe-Geisler
patent: 6192001 (2001-02-01), Weiss et al.
patent: 6256241 (2001-07-01), Mehalel
Meixner et al., “Weak Write Test Mode: An SRAM Cell Stability Design For Test Technique”, International Test Conference, Paper BP, IEEE, 0-7803-4209-7/1997, pp. 1043-1052.
Dinh Son T.
Fish & Richardson P.C.
Intel Corporation
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