Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-03-03
2002-09-24
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
06457151
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a waveform controller for generating various waveforms for an IC tester.
2. Description of the Related Art
Explanation is presented with reference to the figures regarding the prior art.
Explanation is first presented regarding an embodiment of a semiconductor IC tester described in Japanese Patent Laid-open No. 110357/95 as an example of a prior-art waveform controller for an IC tester.
FIG. 1
is a circuit diagram showing the construction of the prior art, and
FIG. 2
is a chart showing the waveform generated by the prior art.
The three edge signals T
1
-T
3
are each outputted at times corresponding to a desired timing edge by a timing generator (not shown). A control signal transmitted from waveform memory (not shown) is supplied to another terminal of AND gate
12
not shown in the figure. The various waveforms for an IC tester are produced by the time settings of signals T
1
-T
3
and the content of waveform memory. Here, waveform memory stores waveform data for forming waveforms.
Signals T
1
-T
3
pass through skew variable regulators
11
1
-
11
3
, respectively, and are inputted to AND gates
12
S and
12
R. The output from the AND gates
12
S are transmitted to OR gate
14
S through a respective skew regulator
13
S. The output from the AND gates
12
R are similarly transmitted to OR gate
14
R through skew regulators
13
R. A set signal is outputted from OR gate
14
S, and a reset signal is outputted from OR gate
14
R.
Signal T
3
is also outputted as signal DREL through skew variable regulator
11
3
, AND gate
12
3
, and skew regulator
13
3
. Signal T
4
is outputted as signal DRET through skew variable regulator
11
4
, AND gate
12
4
, and skew regulator
13
4
. Signals T
5
and T
6
are both used as strobe signals.
In a per-pin tester of the prior art, since waveforms are generated to output three edge signals for set signals and three edge signals for reset signals in each cycle as shown in
FIG. 2
, as for SBC (Surrounded by Complement) waveforms to a driver, three edge signals T
1
-T
3
of
FIG. 1
are split into two to obtain each set and reset signals. As a result, two systems of skew regulators must be provided for one edge signal.
SUMMARY OF THE INVENTION
In view of the problem of the prior art, it is an object of the present invention to provide a waveform controller for an IC tester with the purpose of decreasing the number of skew regulators to half or fewer than the number used in the prior art and thus reducing both circuit scale and power consumption.
As a solution to the above-described problem, the present invention provides a waveform controller for an IC tester that includes selectors and OR circuits for inserting strobe-signal edge signals into the driver signal system, and thus allows an edge signal for strobes to be used as a driver signal edge for driver pins.
The present invention allows the number of provided skew regulators to be reduced to half the number or fewer than are used in the prior art by using strobe-signal edge signals as driver waveform edges when using for pins dedicated to the driver, and the invention therefore has the effect of reducing both circuit scale and power consumption.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of the present invention.
REFERENCES:
patent: 4497056 (1985-01-01), Sugamori
patent: 5291449 (1994-03-01), Dehara
patent: 5590137 (1996-12-01), Yamashita
patent: 5978949 (1999-11-01), Terayama
Advantest Corporation
Chung Phung M.
Knobbe Martens Olson & Bear LLP
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