Watchpoint engine for a pipelined processor

Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...

Reexamination Certificate

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Details

C712S219000, C714S034000, C714S039000

Reexamination Certificate

active

06829701

ABSTRACT:

BACKGROUND
This invention relates to generation of watchpoints for a pipelined processor.
Code developed for complex integrated circuit devices such as pipelined processors typically requires extensive debugging. It is helpful to generate watchpoints that monitor the propagation of instructions through the processor pipeline. For this reason, a watchpoint engine can be provided to extract state information from the processor pipeline and provide the state information to a control unit for event handling. In this manner, application developers can verify proper code operation and thereby debug code developed for the processor.


REFERENCES:
patent: 5371894 (1994-12-01), DiBrino
patent: 5644742 (1997-07-01), Shen et al.
patent: 6349371 (2002-02-01), Ramanadin et al.
patent: 6477683 (2002-11-01), Killian et al.
patent: 6557119 (2003-04-01), Edwards et al.
patent: 0 992 905 (2000-04-01), None
“Internal instruction frequency monitoring”, IBM Technical Disclosure Bulletin, IBM Corp., 35(1B):246-248, Jun. 1992 (XP000309047).

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