Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-09-19
2004-09-07
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S203000, C257S207000, C257S208000, C324S500000, C324S537000, C324S765010
Reexamination Certificate
active
06787801
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a wafer with a plurality of integrated circuits, which are arranged in rows and columns in such a way that interspaces result. The individual integrated circuits can be separated from one another in the area of the interspaces after being tested with an external test system. Additional circuit parts are integrated into the interspaces, each formed with at least one connecting line with an associated integrated circuit via which a function of the integrated circuit can be controlled, and on each of which at least one contact land is provided with which a connection to the external test system can be made.
Current integrated circuits can be constructed very complexly and comprehensively, so that intermediate measurements to check functions or parameters can be complicated and very difficult. In particular at the wafer stage, when the integrated circuits arranged in rows and columns have not yet been separated, i.e., the wafer has not yet been diced, making contact by using a so-called needle card for testing the integrated circuit is possible only to a limited extent, since access to specific circuit parts is often very difficult because of the compact geometries and the close conductor track spacings.
That problem occurs, for example, in the case of memory circuits such as DRAMs (Dynamic Random Access Memory) or similar circuits. There, inter alia, the memory cells have to be checked for example for short circuits or interruptions, the current consumption, internal voltage generators and so on. In particular, testing the current consumption is very difficult, since the conductor tracks of the integrated circuit (IC) cannot be interrupted briefly for a direct current measurement.
The integrated circuit generally also has many control functions. The appropriate test modes, therefore, have to be generated accordingly by the external test system and have to be sent to the integrated circuit at the correct timing cycle rate.
In order to solve the problems, hitherto, for example, specific monitor pads, as they are known, were integrated onto the chip and can be activated or deactivated by means of an appropriate test mode. These monitor pads have an internal chip connection to the integrated circuit and permit, inter alia, a voltage to be fed in, which is supplied by a test system for the desired test function. Making contact with the monitor pads is carried out via a needle card which is matched to the integrated circuit, so that all the necessary voltages, currents or else data words can be transmitted to the integrated circuit or read out from the latter via its contact needles. In some cases, the contact needles also have to be placed directly on the very narrow conductor tracks in order to be able to carry out the desired tests.
Apart from the fact that the sensitive conductor tracks can be damaged, measurement errors may also be included, since the ground level can also be raised by impressing a current or voltage, and voltage drops can occur along the contacts.
Added to this is the fact that, for example in the case of one or more short circuits on a wafer, the current loading can rise enormously, so that this test is made more difficult, since the contact needles and even the conductor tracks are able to cope with only a specific maximum current without being damaged.
Furthermore, it is disadvantageous that, in such a case, the wafer may be heated up to a great extent locally which, depending on the circuit part, can lead to undesired thermal effects such as mechanical stresses, piezoelectric effects and so on, with corresponding erroneous behavior.
The practice of integrating test circuits into the interspace between two chips, the so-called kerf, has also been disclosed. These test circuits have appropriate measuring or contact lands, with which contact can likewise be made by special measuring devices, so that the test system can likewise use these auxiliary circuits for testing the integrated circuits.
A wafer forming the genus of this disclosure is found in U.S. Pat. No. 5,929,650. There, the wafer has a plurality of integrated circuits arranged in rows and columns in such a way that interspaces result. The individual integrated circuits can be separated from one another by dicing along the interspaces (i.e., kerfs) after being tested with an external test system. In the case of the prior art wafer, an additional circuit part is provided in the kerf area for the functional control of the integrated circuits in the individual wafer chips for the purpose of testing. Each of the additional circuit parts comprise at least one connecting line with an associated integrated circuit via which a function of the integrated circuit can be controlled, and on each of which at least one contact land is provided with which a connection to the external test system can be made.
U.S. Pat. No. 5,059,899 also discloses a wafer having a voltage-blocking circuit which is used for the purpose of preventing short circuits arising from the cut-up test conductor tracks after the wafer has been cut up into individual chips. Furthermore, a wafer with an intermediate driver in the kerf area is presented in U.S. Pat. No. 5,899,703.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a wafer with additional circuit parts in the kerf are for testing integrated circuits on the wafer, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which, in simple terms, provides an improved wafer design for testing integrated circuits on the wafer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a wafer, comprising:
a plurality of integrated circuits arranged in rows and columns and forming interspaces therebetween, along which the individual integrated circuits are separated from one another after testing with an external test system;
additional circuit parts integrated in the interspaces;
at least one connecting line connecting each of the additional circuit parts with a respectively associated one of the integrated circuits for controlling a function of the integrated circuit;
at least one contact land formed on each the additional circuit part for connecting the additional circuit part with an external test system;
each the additional circuit part having an intermediate driver configured to disconnect a voltage supplied from the external test system via the additional circuit part to the associated the integrated circuit from an internal voltage of the integrated circuit.
In other words, in the wafer design according to the invention, additional circuit parts, which are formed in the kerf area, are used for testing the integrated circuits on the wafer, it being possible, via at least one connecting line, for functions of an associated integrated circuit to be controlled, such as the activation or deactivation of a voltage generator or the like. In this case, the additional circuit part comprises an intermediate driver, with which disconnection of the voltage supplied by the test system from an internal voltage of the integrated circuit is achieved. As a result, an internal generator can be switched off and a test voltage can be applied externally to a location envisaged on the integrated circuit. In this way, important functions such as the functional capability, the current and voltage behavior, short circuits and so on may advantageously be assessed.
In accordance with an added feature of the invention, the additional circuit part has a measuring device with which a specific voltage of the integrated circuit can be measured directly. Voltage drops, caused by long lines to the test system or high contact resistances at the contact lands, are effectively avoided.
In accordance with an additional feature of the invention, the system is configured for a current measurement, which can likewise be carried out with an appropriate measuring device of the additional circuit part. As a result, for ex
Fischer Helmut
Morgan Alan
Infienon Technologies AG
Mondt Johannes
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