Wafer scale testing using a 2 signal JTAG interface

Details Wafer scale testing using a 2 signal JTAG interface Wafer scale testing using a 2 signal JTAG interface

2008-07-18

2009-08-04

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S715000, C714S727000, C324S763010

Reexamination Certificate

active

07571365

ABSTRACT:
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

REFERENCES:
patent: 6597198 (2003-07-01), Haycock et al.
patent: 6653957 (2003-11-01), Patterson et al.
patent: 6988232 (2006-01-01), Ricchetti et al.
SN54LVT8996, SN74LVT8996 3.3-V 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) Tap Transceivers, scbs686a-Apr. 1997, Revised Dec. 1999, Texas Instruments Inc. pp. 1-41.
SCANPSC 11 of Scan Bridge Hierarchical and Multidrop Addressable JTAG Port (1EEEI 149.1 System Test Support), National Semiconductor Corporation, Oct. 1999, pp. 1-29.

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