Wafer scale testing using a 2 signal JTAG interface

Details Wafer scale testing using a 2 signal JTAG interface Wafer scale testing using a 2 signal JTAG interface

2011-03-08

2011-03-08

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S715000, C714S733000

Reexamination Certificate

active

07904774

ABSTRACT:
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

REFERENCES:
patent: 6073254 (2000-06-01), Whetsel
patent: 6242269 (2001-06-01), Whetsel
patent: 6543020 (2003-04-01), Rajski et al.
patent: 6988232 (2006-01-01), Ricchetti et al.
patent: 7421633 (2008-09-01), Whetsel
Bhatia, S.; , “Test compaction by using linear-matrix driven scan chains,” Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on , vol., no., pp. 185-190, Nov. 3-5, 2003 doi: 10.1109/DFTVS.2003.1250111.
Zacharia, N.; Rajski, J.; Tyszer, J.; Waicukauski, J.A.; , “Two-dimensional test data decompressor for multiple scan designs ,” Test Conference, 1996. Proceedings., International , vol., no., pp. 186-194, Oct. 20-25, 1996 doi: 10.1109/TEST.1996.556961.

Affiliated with

Also associated with

Rating

Wafer scale testing using a 2 signal JTAG interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer scale testing using a 2 signal JTAG interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer scale testing using a 2 signal JTAG interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2763155