Wafer-leveled chip packaging structure and method thereof

Details Wafer-leveled chip packaging structure and method thereof Wafer-leveled chip packaging structure and method thereof

2007-11-13

2007-11-13

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C438S106000

Reexamination Certificate

active

11186840

ABSTRACT:
This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

REFERENCES:
patent: 7060526 (2006-06-01), Farnworth et al.

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