Wafer level testing and bumping process

Details Wafer level testing and bumping process Wafer level testing and bumping process

2006-06-20

2006-06-20

Luu, Chuong Anh (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

Reexamination Certificate

active

07064445

ABSTRACT:
A wafer level testing and bumping process is provided. A plurality of test pads serving as testing point for testing and analyzing the circuits within the wafer is formed on the active surface of the wafer. The test pads are electrically connected to the flip-chip bonding pads respectively. The test pads are positioned on the peripheral section of the active surface. The tip of probe pins hanging from a cantilever probe card touches the test pads so that the wafer can be tested through the probe pins to obtain some test results. Whether to cut a particular fuse line underneath a fuse window by aiming a laser beam at the fuse window can be determined according to the test results. Finally, a passivation layer and bumps are formed on the active surface of the wafer and then the wafer is cut to form a plurality of single chips ready for performing subsequent packing processes.

REFERENCES:
patent: 6674159 (2004-01-01), Peterson et al.
patent: 6803659 (2004-10-01), Suwa et al.

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