Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2007-05-08
2007-05-08
Parekh, Nitin (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000, C257S774000, C257S737000, C257SE23145
Reexamination Certificate
active
10899175
ABSTRACT:
A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.
REFERENCES:
patent: 6239495 (2001-05-01), Sakui et al.
patent: 6577013 (2003-06-01), Glenn et al.
patent: 6611052 (2003-08-01), Poo et al.
patent: 6809421 (2004-10-01), Hayasaka et al.
patent: 2004/0080040 (2004-04-01), Dotta et al.
patent: 2004/0188819 (2004-09-01), Farnworth et al.
patent: 2005/0242422 (2005-11-01), Klein et al.
patent: 10223833 (1998-08-01), None
patent: 2002100727 (2002-04-01), None
patent: 2002-217356 (2002-08-01), None
patent: 2002-0024624 (2002-04-01), None
Korean Office Action Issued Nov. 18, 2005.
Kim Gu-Sung
Lee Kang-Wook
Oh Se-Yong
Song Young-Hee
Harness & Dickey & Pierce P.L.C.
Parekh Nitin
Samsung Electronics Co,. Ltd.
LandOfFree
Wafer level stack structure for system-in-package and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wafer level stack structure for system-in-package and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer level stack structure for system-in-package and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3811340