Wafer-level stack package and method of fabricating the same

Details Wafer-level stack package and method of fabricating the same Wafer-level stack package and method of fabricating the same

2011-03-01

2011-03-01

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S774000, C257SE23145, C257SE23174, C257SE21577, C257SE21649, C438S667000

Reexamination Certificate

active

07897511

ABSTRACT:
A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

REFERENCES:
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patent: 2005-0021078 (2005-03-01), None
patent: 2005-0118904 (2005-12-01), None

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