Wafer level packaging

Details Wafer level packaging Wafer level packaging

2008-05-13

2010-10-26

Blum, David S (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S462000, C438S612000, C438S667000, C257SE23023, C257SE23011

Reexamination Certificate

active

07820484

ABSTRACT:
Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.

REFERENCES:
patent: 4871418 (1989-10-01), Wittlinger et al.
patent: 4961821 (1990-10-01), Drake et al.
patent: 5166097 (1992-11-01), Tanielian
patent: 5825076 (1998-10-01), Kotvas et al.
patent: 6096635 (2000-08-01), Mou et al.
patent: 7712211 (2010-05-01), Chia et al.
patent: 0802416 (1997-10-01), None
patent: 61064176 (1986-04-01), None

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