Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2009-05-29
2011-12-06
Fourson, III, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S617000, C257SE21506, C257SE21509
Reexamination Certificate
active
08071470
ABSTRACT:
A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed.
REFERENCES:
patent: 5328079 (1994-07-01), Mathew et al.
patent: 5496775 (1996-03-01), Brooks
patent: 5559054 (1996-09-01), Adamjee
patent: 6017812 (2000-01-01), Yonezawa et al.
patent: 6098868 (2000-08-01), Mae et al.
patent: 6211461 (2001-04-01), Park et al.
patent: 6242283 (2001-06-01), Lo et al.
patent: 6277669 (2001-08-01), Kung et al.
patent: 6387795 (2002-06-01), Shao
patent: 6407333 (2002-06-01), Schroen
patent: 6420256 (2002-07-01), Ball
patent: 6452238 (2002-09-01), Orcutt et al.
patent: 6885101 (2005-04-01), Storli
patent: 6934065 (2005-08-01), Kinsman
patent: 2002/0058403 (2002-05-01), Farnworth
patent: 2008/0081399 (2008-04-01), Takano et al.
patent: 2009/0206480 (2009-08-01), Lam
patent: 1211854 (2005-07-01), None
patent: 101154602 (2008-04-01), None
Garrou “Wafer-Level Packaging Has Arrived”, IEEE Components, Packaging and Manufacturing Technology Society, Semiconductor Society, Oct. 1, 2000.
Garrou et al “Fundamentals of Wafer-Level Packaging” Fundamentals of Microsystems Packaging, pp. 398-418, Chapter 10, Copyright 2001, MCGraw-Hill, New York, New York.
Levine et al “Copper Stud Bumping for Flip-Chip Applications” www.semiconductor.net/index.asp?layout=articlePrint&articleID=CA6339170, Jun. 1, 2006, printed Dec. 14, 2007, p. 8.
Topper “The Wafer-Level Packaging Evolution”, Oct. 1, 2004, Reed Business Information.
Keong Lau Choong
Khor Lily
Wai Yong Lam
Carsem (M) SDN. BHD.
Fourson, III George
Kilpatrick Townsend & Stockton LLP
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