Wafer level package having redistribution interconnection...

Details Wafer level package having redistribution interconnection... Wafer level package having redistribution interconnection...

2006-06-08

2009-06-09

Le, Thao X (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S701000, C438S106000, C438S121000, C438S125000

Reexamination Certificate

active

07545027

ABSTRACT:
A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

REFERENCES:
patent: 6362087 (2002-03-01), Wang et al.
patent: 6730589 (2004-05-01), Hashimoto
patent: 7196000 (2007-03-01), Lee et al.
patent: 2002/0162998 (2002-11-01), Okuda et al.
patent: 2000-286283 (2000-10-01), None
patent: 10-2001-0004529 (2001-01-01), None
patent: 10-2005-0011404 (2005-01-01), None

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