Wafer level package having a stress relief spacer and...

Details Wafer level package having a stress relief spacer and... Wafer level package having a stress relief spacer and...

2009-07-01

2010-11-23

Malsawma, Lex (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S773000, C257SE23023, C257SE23168

Reexamination Certificate

active

07838992

ABSTRACT:
In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

REFERENCES:
patent: 5646067 (1997-07-01), Gaul
patent: 5648684 (1997-07-01), Bertin et al.
patent: 5925924 (1999-07-01), Cronin et al.
patent: 2003/0194860 (2003-10-01), Nemoto
patent: 2005/0003649 (2005-01-01), Takao
patent: 2002-198463 (2002-07-01), None
patent: 2003-017621 (2003-01-01), None
“Wafer Level Package Having a Stress Relief Spacer and Manufacturing Method Thereof,” Specification, Drawings, and Prosecution History of U.S. Appl. No. 11/355,545, filed Feb. 15, 2006, by Hyun-Soo Chung, et al., which is stored in the United States Patent and Trademark Office (USPTO) Image File Wrapper (IFW) system.

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