Wafer level integration package

Details Wafer level integration package Wafer level integration package

2009-06-26

2010-11-30

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

With means to shield device contained in housing or package...

C257S696000, C257S698000, C257SE23114

Reexamination Certificate

active

07843042

ABSTRACT:
A semiconductor package has a first conductive layer formed on a top surface of a substrate. A conductive via is formed between the first conductive layer and a bottom surface of the substrate. A semiconductor component is mounted to the substrate and electrically connected to the first electrical contact pad. The semiconductor component can be a flip chip semiconductor device, wire bond semiconductor device, or passive component. An encapsulant is deposited over the semiconductor component. The encapsulant extends into a channel formed on a side of the substrate from the top surface to the bottom surface of the substrate. An interconnect structure is formed over the bottom surface of the substrate. A heat spreader structure can be disposed over the semiconductor component. An EMI shield can be disposed over the semiconductor component. A plurality of semiconductor components can be stacked in a package-in-package arrangement.

REFERENCES:
patent: 6958544 (2005-10-01), Sunohara
patent: 2001/0004130 (2001-06-01), Higashi et al.
patent: 2002/0001922 (2002-01-01), Farnworth
patent: 2004/0156172 (2004-08-01), Lin et al.
patent: 2005/0121768 (2005-06-01), Edelstein et al.
patent: 2006/0275946 (2006-12-01), MacNamara et al.

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