Wafer level chip scale package, method of manufacturing the...

Details Wafer level chip scale package, method of manufacturing the... Wafer level chip scale package, method of manufacturing the...

2007-12-04

2010-11-09

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S786000, C257SE23020, C257S778000

Reexamination Certificate

active

07830017

ABSTRACT:
Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

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English language abstract of Japanese Publication No. 11-046054.
English language abstract of Korean Publication No. 2001-0061782.
English language abstract of Korean Publication No. 10-0596452.

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