Wafer level chip scale package

Details Wafer level chip scale package Wafer level chip scale package

2005-05-31

2005-05-31

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S690000, C257S701000, C257S702000, C257S737000, C257S738000, C257S780000, C257S778000, C257S773000, C257S786000, C257S774000

Reexamination Certificate

active

06900532

ABSTRACT:
A wafer level fabricated integrated circuit package having an air gap formed between the integrated circuit die of the package and a flexible circuit film located over and conductively attached to the die though raised interconnects formed on the die is described. The flexible circuit film further includes routing conductors that connect inner landings on the bottom surface of the flexible circuit film with outer landings on the top surface of the flexible circuit film. The outer landings are offset a horizontal distance from the inner landings. In some embodiments, contact bumps are formed on the outer landings of the flexible circuit film layer for use in connecting the package to other substrates. The wafer level chip scale package provides a highly compliant connection between the die and any other substrate that the die is attached to.

REFERENCES:
patent: 5300402 (1994-04-01), Card et al.
patent: 5477160 (1995-12-01), Love
patent: 5508229 (1996-04-01), Baker
patent: 5518964 (1996-05-01), DiStefano et al.
patent: 5677576 (1997-10-01), Akagawa
patent: 5691041 (1997-11-01), Frankeny et al.
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5892271 (1999-04-01), Takeda et al.
patent: 5915170 (1999-06-01), Raab et al.
patent: 5933712 (1999-08-01), Bernhardt et al.
patent: 5936843 (1999-08-01), Ohshima et al.
patent: 5990546 (1999-11-01), Igarashi et al.
patent: 6002168 (1999-12-01), Bellaar et al.
patent: 6020220 (2000-02-01), Gilleo et al.
patent: 6077757 (2000-06-01), Mizuno et al.
patent: 6081026 (2000-06-01), Wang et al.
patent: 6323058 (2001-11-01), Murakamz et al.

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