Wafer level bumping process

Details Wafer level bumping process Wafer level bumping process

2007-05-29

2007-05-29

Ha, Nathan W. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S737000

Reexamination Certificate

active

10876582

ABSTRACT:
A bumping process mainly comprises the following steps. Initially, a wafer having a plurality of bonding pads and a passivation layer with passivation openings exposing the bonding pads is provided. Next, a first dielectric layer with first openings and second openings is disposed on the wafer. The first openings and second openings expose the bonding pads and the portions of the passivation layer respectively. Afterwards, a patterned first electrically conductive layer is formed over the first dielectric layer and the bonding pads. Then a second dielectric layer is formed over the first dielectric layer and the patterned first electrically conductive layer and exposes the patterned first conductive layer through the second openings to form a plurality of bump pads wherein the bump pads are electrically connected to bonding pads. Next, a second electrically conductive layer is formed over the second dielectric layer and the bump pads. Then, a plurality of bumps are formed on the portions of the second electrically conductive layer covering the bump pads. Finally, the bumps are reflowed and the portions of the second electrically conductive layer covered by the reflowed bumps are remained to form a patterned second electrically conductive layer.

REFERENCES:
patent: 6350668 (2002-02-01), Chakravorty
patent: 6400021 (2002-06-01), Cho
patent: 6455408 (2002-09-01), Hwang et al.
patent: 6541303 (2003-04-01), Akram et al.
patent: 6642136 (2003-11-01), Lee et al.
patent: 6689680 (2004-02-01), Greer
patent: 6869870 (2005-03-01), Lin
patent: 2001/0020737 (2001-09-01), Kwon et al.
patent: 2002/0096764 (2002-07-01), Huang
patent: 2002/0185721 (2002-12-01), Hwang et al.
patent: 2003/0162323 (2003-08-01), Akram et al.
patent: 2004/0094837 (2004-05-01), Greer
patent: 2004/0212102 (2004-10-01), Akram et al.
patent: 2004/0266163 (2004-12-01), Horng
patent: 2005/0048695 (2005-03-01), Chia et al.
patent: 2005/0189650 (2005-09-01), Lee et al.
patent: 2005/0230783 (2005-10-01), Lin
patent: 2005/0236709 (2005-10-01), Eng et al.

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