Wafer integrated with permanent carrier and method therefor

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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Details

C257SE23123, C257SE21502, C257SE27026, C257SE27027, C438S118000, C438S115000, C438S458000, C438S459000, C438S626000

Reexamination Certificate

active

07880293

ABSTRACT:
A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.

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patent: 6040235 (2000-03-01), Badehi
patent: 6342406 (2002-01-01), Glenn et al.
patent: 6646289 (2003-11-01), Badehi
patent: 6911392 (2005-06-01), Bieck et al.
patent: 7160478 (2007-01-01), Leib et al.
patent: 2004/0262735 (2004-12-01), Higashi et al.
patent: 2006/0231750 (2006-10-01), Chao et al.
patent: 2007/0172985 (2007-07-01), Huang et al.

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