Wafer having scribe lanes suitable for sawing process,...

Details Wafer having scribe lanes suitable for sawing process,... Wafer having scribe lanes suitable for sawing process,...

2006-09-11

2008-10-14

Zarneke, David A (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

C257SE23001, C257SE23002

Reexamination Certificate

active

07436047

ABSTRACT:
A wafer that is less susceptible to chipping or peeling during a sawing process is disclosed. The wafer includes a plurality of chips, scribe lanes formed between the plurality of chips, and a passivation film, which is formed on the plurality of chips and the scribe lanes and has a plurality of perforations, e.g. slit patterns engraved on each scribe lane. A photolithography reticle and method of manufacturing the wafer are also provided.

REFERENCES:
patent: 6441465 (2002-08-01), Lin et al.
patent: 6879019 (2005-04-01), Windlass et al.
patent: 6879025 (2005-04-01), Sasaki et al.
patent: 2005/0101108 (2005-05-01), Genda et al.
patent: 2006/0223234 (2006-10-01), Terayama et al.
patent: 2007/0222037 (2007-09-01), Wu
patent: 1999-00485 (1999-01-01), None
patent: 2003-0001880 (2003-01-01), None
patent: 2005-0010698 (2005-01-01), None
English language abstract of Korean Publication No. 1999-00485.
English language abstract of Korean Publication No. 2003-0001880.
English language abstract of Korean Publication No. 2005-0010698.

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