Wafer fabrication of die-bottom contacts for electronic devices

Details Wafer fabrication of die-bottom contacts for electronic devices Wafer fabrication of die-bottom contacts for electronic devices

1998-06-26

2001-04-24

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S110000, C438S112000, C438S113000, C438S458000, C438S459000, C438S460000, C438S462000, C438S613000, C438S617000

Reexamination Certificate

active

06221751

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of electronic device packaging and fabrication. More particularly, the present invention relates to improved contacts for semiconductors, integrated circuits and other electronic circuits and discrete electronic components.
BACKGROUND OF THE INVENTION
The package of any electronic device must include contacts for transmitting signals providing power and ground connections between the internal circuitry of the device and external circuitry. Simple examples of prior-art contacts include the wire leads protruding from the ends of a discrete diode or resistor, or the metal caps located on the ends of a fuse. On the other hand, a sophisticated electronic device, such as a microprocessor, may require several hundred contacts. Those devices are usually produced in a package having multiple pins for mounting to a printed circuit board via contact holes.
More modern surface mount techniques can be used to connect a device to a printed circuit board without cumbersome pins. The leads of a surface mount device simply flush mount to the surface of a printed circuit board, such as the motherboard of a personal computer system, onto which the device is attached by soldering to contact wires or conductors. Surface mount leads do not penetrate through the circuit board like a conventional packages having pins, making them efficient to use in production.
Referring now to
FIG. 1
, a prior-art integrated circuit that is surface mounted to a circuit board is illustrated. This integrated circuit includes a silicon (Si) based integrated circuit
101
. Insulating film
102
coats the underside of circuit
101
to protect and passivate it. Epoxy layer
103
and a silicon cap
104
cover circuit
101
. Epoxy layer
103
and silicon cap
104
also cover metal bridge
105
.
Metal bridge
105
electrically connects circuit
101
to silicon post
106
. Epoxy section
111
mechanically secures circuit
101
, metal bridge
105
and silicon post
106
. Nickel (Ni) plate
107
covers silicon post
106
and forms a butt-joint with metal bridge
105
. Nickel plate
107
is electrically coupled to silicon post
106
and metal bridge
105
. Nickel plate
107
provides the integrated circuit with a connection point to external circuitry.
This prior-art contact comprises:
1) metal bridge
105
,
2) silicon post
106
,
3) nickel plate
107
, and
4) epoxy section
111
.
As illustrated in
FIG. 1
, the contact of the integrated circuit has been soldered to circuit board conductor
109
with solder fillet
108
. Circuit board conductor
109
has been formed onto circuit board substrate
110
.
The contact for the integrated circuit illustrated in
FIG. 1
provides for various advantages. For example, nickel plate
107
covers the sidewalls of silicon post
106
, which helps to strengthen the bond between the circuit
101
and the circuit board substrate
110
. This is due to the fact that solder can be placed on nickel plate
107
on the sidewalls of silicon post
106
as illustrated in FIG.
1
. It also facilitates inspection during surface mount of the integrated circuit to the circuit board. Whether a good mount is made can be easily confirmed by looking at the solder on the sidewalls of silicon post
106
.
Furthermore, nickel plate
107
extends over the sidewalls of silicon post
106
and contacts the side of metal bridge
105
, forming a butt-joint interface between nickel plate
107
and metal bridge
105
. This provides for an electrical contact between circuit board conductor
109
and circuit
101
.
The butt-joint interface of the integrated circuit contact of
FIG. 1
, however, cannot be formed with much certainty or control over its resulting reliability or bonding adhesion between nickel plate
107
and metal bridge
105
. There are a number of reasons for this. The physical surface of the side of metal bridge
105
might not be flat enough to ensure a reliable bond at this butt-joint interface. Furthermore, the side of metal bridge
105
is difficult to clean because of its location on the side of the wafer. The bond at this butt-joint interface therefore might be weakened If the side of metal bridge
105
is not flat or has not been thoroughly cleaned.
The formation of this butt-joint interface also limits the materials that can be used for nickel plate
107
and metal bridge
105
. This is so because metal bridge
105
and nickel plate
107
can comprise more than one metal layer. The bonding layer of nickel plate
107
then has to be formed so as to bond with each metal layer at the side of metal bridge
105
in order to form an effective contact. Accordingly, the selection of materials that can be used for metal bridge
105
and for the bonding layer of nickel plate
107
is limited.
FIG. 2
shows a prior-art contact that avoids a butt-joint by using a wrap-around flange contact. Silicon based circuit
101
, insulating film
102
, epoxy layer
103
, silicon cap
104
, metal bridge
105
, silicon post
106
, solder filet
108
, circuit board conductor
109
, circuit board substrate
110
, and epoxy section
111
are similar to that of the above described butt-joint contact. However, wrap around nickel plate
112
and metal bridge
105
have a horizontal flange interface
113
. While the wrap around flange avoids the problems associated with a butt-joint, it is still a relatively complex design, requiring a rather involved series of processing steps and a relatively large amount of wafer area dedicated to contact fabrication.
SUMMARY AND OBJECTS OF THE INVENTION
An object of the present invention is to simplify the process of fabricating contacts for electronic devices.
Another object is to increase the simplicity and the reliability of contacts for electronic devices.
A further object is to increase the wafer packing density of an electronic circuit by reducing the substrate area that is used for fabricating the device's contacts.
Another object is to provide contacts that have physical and electronic properties applicable to varied types of electronic devices.
Accordingly, a contact for an electronic device is described that comprises a standoff on the bottom surface of the substrate and a lower wire that extends from the standoff to an upper wire that runs on an encapsulant protrusion.
Such a contact is fabricated by forming a trench in the top surface of a substrate. The trench may be located near the edge of an electronic circuit or discrete component formed using or attached to the substrate. Optionally, an insulation layer is formed that has a through hole at a connection point within the circuit or component, and that ends part way through the trench. An upper wire is formed that runs from the connection point into the trench. The top of the substrate is encapsulated, forming an encapsulant protrusion in the trench.
In one embodiment, the substrate is selectively thinned from the bottom, exposing part of the bottom surface of the upper wire. In the next step, a standoff is formed below the bottom surface of the substrate. Alternatively, the standoff can be formed from the substrate during the selective thinning step. A lower wire is formed that runs on the bottom of the substrate from the exposed portion of the upper wire and onto the standoff.
In another embodiment, there is no top-surface trench. Rather, the trench in which the upper wires and the lower wires connect is formed from the bottom of the substrate after it has been encapsulated.
Optionally, the thinning of the substrate's bottom surface leaves a portion of the bottom surface of the substrate substantially co-planar with the bottom of the contacts.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description below.


REFERENCES:
patent: 4870475 (1989-09-01), Endo et al.
patent: 4931410 (1990-06-01), Tokunaga et al.
patent: 5071792 (1991-12-01), Van Vonno et al.
patent: 5280194 (1994-01-01), Richards et al.
patent: 5306942 (1994-04-01), Fuji
patent: 5353498 (1994-1

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