Wafer edge seal ring structure

Details Wafer edge seal ring structure Wafer edge seal ring structure

1996-12-16

1998-03-03

Jackson, Jerome

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

438703, 438782, 438783, 257618, 257758, H01L 214763, H01L 2302, H01L 2329, H01L 2331

Patent

active

057233853

ABSTRACT:
A wafer edge seal ring structure is disclosed to provide reduced particulate contaminant generation during wafer processing of high density integrated circuits. The structure is formed by delimiting the deposition of layers at the peripheral edges of wafers. It is shown that as each layer is deposited and then essentially trimmed back from the edge of the wafer through a judicious use of mask and etching, and/or edge-bead rinsing (EBR) and later sealed by wafer edge exposure (WEE), the otherwise present abnormal growth of layers are prevented from building up into protrusions at the edge of wafer that later peel or break up to form particulate matter and fine dust. The method, which is also disclosed, teaches how each layer is recessed at appropriate distances from the wafer edge and how the whole ring structure is sealed against attacking particles.

REFERENCES:
patent: 5425846 (1995-06-01), Koze et al.
patent: 5426073 (1995-06-01), Imaoka et al.
patent: 5593925 (1997-01-01), Yamaha

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