Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1999-01-28
2001-07-24
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S694000, C438S778000, C438S783000
Reexamination Certificate
active
06265328
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of integrated circuits. More particularly, the present invention provides a technique for forming substrates using a novel edge engineering technique. This invention is illustrated using, for example, silicon-on-insulator (“SOI”) wafers, but can be applied to other types of substrates such as bulk substrates, patterned substrates, multi-layered substrates, and others.
Integrated circuits are fabricated on chips of semiconductor material. These integrated circuits often contain thousands, or even millions, of transistors and other devices. In particular, it is desirable to put as many transistors as possible within a given area of semiconductor material because more transistors typically provide greater functionality, and a smaller chip means more chips per wafer and lower costs. From the development of the integrated circuit at Fairchild Semiconductor by Robert Noyce and Jack Kilby at Texas Instruments to modern day times, industry has always attempted to fabricate more and more devices on a given area of silicon.
Some integrated circuits are fabricated on a slice or wafer, of single-crystal (monocrystalline) silicon, commonly termed a “bulk” silicon wafer. Devices on such “bulk” silicon wafer typically are isolated from each other. A variety of techniques have been proposed or used to isolate these devices from each other on the bulk silicon wafer, such as a local oxidation of silicon (“LOCOS”) process, trench isolation, and others. These techniques, however, are not free from limitations. For example, conventional isolation techniques consume a considerable amount of valuable wafer surface area on the chip, and often generate a non-planar surface as an artifact of the isolation process. Either or both of these considerations generally limit the degree of integration achievable in a given chip. Additionally, trench isolation often requires a process of reactive ion etching, which is extremely time consuming and can be difficult to achieve accurately.
An approach to achieving very-large scale integration (“VLSI”) or ultra-large scale integration (“ULSI”) uses a semiconductor- or silicon-on-insulator (“SOI”) wafer. An SOI wafer typically has a layer of silicon on top of a layer of an insulator material. A variety of techniques have been proposed or used for fabricating the SOI wafer. These techniques include, among others, growing a thin layer of silicon on a sapphire substrate, bonding a layer of silicon to an insulating substrate, and forming an insulating layer beneath a silicon layer in a bulk silicon wafer, which is commonly termed SIMOX. In an SOI integrated circuit, essentially complete device isolation is often achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. An advantage SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer.
SOI offers other advantages over bulk silicon technologies as well. For example, SOI offers a simpler fabrication sequence compared to a bulk silicon wafer. Devices fabricated on an SOI wafer may also have better radiation resistance, less photo-induced current, and less cross-talk than devices fabricated on bulk silicon wafers. Many problems, however, that have already been solved regarding fabricating devices on bulk silicon wafers remain to be solved for fabricating devices on SOI wafers.
That is, numerous limitations exist in the manufacture of SOI wafers. In general, some techniques for fabricating SOI can produce SOI wafers with substantially defect free layers having relatively low thickness variation, but these techniques often produce SOI wafers in relatively low yield and at high cost, as compared to bulk wafers. Other techniques can produce high yields. These techniques, however, often produce poor quality films.
From the above, it is seen that an improved technique for manufacturing a substrate such as, for example, an SOI wafer and others is highly desirable.
SUMMARY OF THE INVENTION
According to the present invention, a technique including a method and device for fabricating and shaping an exclusion region or for clearing layer(s) on a substrate is provided. In an exemplary embodiment, the present invention uses a stream of fluid to selectively remove or “ablate” a portion of a film of material on a substrate. In other embodiments, the present invention can use a directional beam of plasma or “plug” of plasma to ablate a portion of a film of a material on a substrate. In some of these embodiments, the substrate is rotated to expose all locations of an outer periphery of the substrate to the stream of fluid or plug of plasma for ablation purposes.
In a specific embodiment, the present invention provides a novel method for fabricating a substrate, e.g., SOI. The method includes a step of providing a substrate, which has an overlying thickness of material (e.g., SiO
2
, silicon, germanium) on the substrate. The thickness of material has a surface thereon, which is substantially planar. The thickness of material also extends to an outer periphery of the substrate. The method also includes a step of rotating the substrate about a center region (e.g., geometric center point) of the substrate such that the surface moves in parallel alignment relative to a fixed plane. A stream of material (i.e., acid, base, abrasive) is applied to an outer portion of the thickness of material as the substrate rotates to ablate an outer peripheral portion of the thickness of material that contacts the stream of material.
In an alternative embodiment, the present invention provides an apparatus for abating edge material from a substrate, e.g., SOI. The apparatus includes, among other elements, a housing and a rotatable member coupled to the housing. The rotatable member is a susceptor or platen, which has a relatively flat surface for securing a substrate. A movable dispensing head is coupled to the housing and is overlying the rotatable member, which has a workpiece (e.g., substrate, SOI) thereon. The movable dispensing head is operable to emit a stream of directed fluid to one or more locations of the susceptor. The apparatus also includes a fluid source, which is coupled to the movable dispensing head. The fluid source provides fluid to ablate material from the substrate. In a specific embodiment, the fluid can be a combination of compounds to form an acidic fluid, which etches or ablates a portion of the rotating substrate.
Numerous advantages are achieved over conventional techniques by way of the present invention. In some embodiments, the present invention provides a technique that is substantially free from the use of masking layers or photomasking layers. By way of substantially no photomasking, the present invention is cleaner and more cost effective than conventional techniques that require the use of photomasks. It also eliminates the possibility of leaving hydrocarbon residues after photoresist removal. The present invention can also be applied during and after a number of process steps. Accordingly, the present invention is more flexible and cleaner than pre-existing techniques. In other embodiments, the present invention provides for the accurate control of ablated regions to form and shape exclusionary regions. These and other advantages or benefits are described throughout the present specification and more particularly below.
These and other embodiments of the present invention, as well as other advantages and features, are described in more detail in conjunction with the text below and attached Figs.
REFERENCES:
patent: 5897379 (1999-04-01), Ulrich et al.
patent: 6033988 (2000-03-01), Hirano
patent: 8-107091 (1996-04-01), None
Cheung Nathan
Eng William G.
Henley Francois J.
Malik Igor J.
Bowers Charles
Kilday Lisa
Silicon Genesis Corporation
Townsend and Townsend / and Crew LLP
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