Wafer burn-in test circuit and method for testing a semiconducto

Static information storage and retrieval – Read/write circuit – Testing

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365210, 36523006, G11C 700

Patent

active

060260386

ABSTRACT:
A wafer burn-in test circuit of a semiconductor memory device having a plurality of memory cells arranged in a row/column matrix, is provided, including: a sub word line driver connected to first and second word line groups each connected to true cells and complement cells forming the memory cells, and responding to a predecoded low address; and first and second power lines respectively supplying power to the corresponding first and second power line groups by a switching operation of the sub word line driver, wherein a ground power source is applied to the first and second power lines during a normal operation, and the ground power source and a step-up power source are alternately applied to the first and second power lines during a wafer burn-in test operation.

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patent: 5757228 (1998-05-01), Furutani et al.
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