Wafer burn-in test circuit and a method thereof

Details Wafer burn-in test circuit and a method thereof Wafer burn-in test circuit and a method thereof

1996-09-16

1998-08-04

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36523006, 371 211, G11C 2900, G11C 700

Patent

active

057904650

ABSTRACT:
A burn-in test circuit of a semiconductor memory device with a first test circuit having output terminals connected to input terminals of a first half of plurality of word line drivers. A second test circuit has output terminals connected to input terminals of a second half of the plurality of word line drivers. The first and second tests circuits are sequentially activated to perform a burn-in test for all the memory cells.

REFERENCES:
patent: 5265057 (1993-11-01), Furuyama et al.
patent: 5467356 (1995-11-01), Choi
patent: 5590079 (1996-12-01), Lee et al.

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