Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-03-22
2001-12-04
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S189110
Reexamination Certificate
active
06327682
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates in general to semiconductor memories and in particular to burn-in testing of DRAM (dynamic random access memory) and FeRAM (ferroelectric random access memory) memory chips.
2. Description of Related Art
With the increased density and complexity of semiconductor devices, the elements of the circuitry are becoming increasingly smaller and more prone to defects. Smaller sized defects are increasingly more important as semiconductor device elements become smaller. The use of burn-in testing to sort out devices with defects is important for detecting defective units, and a mainstay of semiconductor memory processing.
In U.S. Pat. No. 5,657,282 (Lee) a stress circuit and a method of applying a stress voltage is described. During test a first and second stress voltage is applied to physically adjacent word lines, and the state of a selected memory cell is sensed. In U.S. Pat. No. 5,467,356 (Choi) a burn-in enable circuit and a burn-in test method is shown. A high external voltage exceeding the external power voltage is applied to a semiconductor memory device that is detected by a burn-in enable circuit and causes a high stress voltage to be applied to all access transistors during burn-in. In U.S. Pat. No. 5,357,193 (Tanaka et al.) is described a memory device with a high voltage stress applying circuit and which reduces the number of test pads required on the memory chip. In U.S. Pat. No. 5,155,701 (Komori et al.) a method is described for testing inferior data retention of a defective EPROM memory cell.
In DRAM testing as with other high density semiconductor devices, improving the throughput of the semiconductor process is important to reducing manufacturing cost. Being able to screen out defective chips early in the process reduces the load on additional required process steps. Detecting defective memory chips at the wafer level provides a means by which the throughput of the manufacturing process can be improve.
SUMMARY OF THE INVENTION
In this invention a burn-in test stress voltage is applied across the storage capacitors in the memory cells of a DRAM or a FeRAM. Although, this burn-in could be applied at the package level, it is applied at the wafer level to allow the detection of weak bits and to allow screening out chips before wafer sorting and chip packaging. This reduces the number of devices processed in subsequent process steps and improves the process throughput of the memory chip.
Three probe pads are added to the memory chip, a burn-in (BI) control pad, a Vpp voltage pad to connect a voltage to the wordline drivers with sufficient power to power on all word lines simultaneously, and a Vcs pad that applies a stress voltage to one side of the storage capacitors of the memory cells. When a memory chip on a wafer is probed and a BI control signal is applied, all word lines are turned on, the reference voltage that is applied to the cell plate during normal operation is disconnected from the storage capacitors of the memory cells, and the memory chip circuitry such as refresh, addressing, read and write circuitry are disabled and put into a static state. The BI control signal turns on a pull down transistor connected to each bit line of the memory chip. The pull down transistors connects each bit line to circuit ground, and when the word lines are activated, the pull down transistor permits a low voltage to be applied to the cell side of the storage capacitor of the memory cells.
The word lines are activated by the burn-in control signal and a Vpp voltage applied to the Vpp pad on the memory chip is used to power the word lines. The Vpp voltage replaces the word line power supply and powers the word line drivers to turn on all word lines which allows the low voltage on the bit lines from the pull down transistors to be connected to the cell side of the storage capacitors. A stress voltage is connected to the reference side of the storage capacitors by a stress voltage applied to the Vcs pad on the memory chip. A switch controlled by the burn-in control signal disconnects a reference voltage used in normal operations from the reference side of the storage capacitor to allow a stress voltage connected to the Vcs pad to be applied to the reference side of the storage capacitors.
During burn-in testing of a DRAM or a FeRAM at the wafer level using the methods of this invention, all word lines are turned on, all bit lines are connected to circuit ground by means of the pull down transistors which in turn connects a low voltage to the cell side of all storage capacitors, and the reference side of each capacitor is connected to an applied external stress voltage. Thus the storage capacitor is stressed to a voltage that is the difference of the stress voltage and the low voltage from the bit lines. This burn-in testing screens out most weak bits before wafer sorting and chip packaging, and improves memory chip throughput by reducing the number of chips that will be tested bad in subsequent test steps in the manufacturing process to produce good memory chips including DRAM and FeRAM product.
REFERENCES:
patent: 5155701 (1992-10-01), Komori et al.
patent: 5282167 (1994-01-01), Tanaka et al.
patent: 5317532 (1994-05-01), Ochii
patent: 5357193 (1994-10-01), Tanaka et al.
patent: 5467356 (1995-11-01), Choi
patent: 5590079 (1996-12-01), Lee et al.
patent: 5638331 (1997-06-01), Cha et al.
patent: 5657282 (1997-08-01), Lee
patent: 5790465 (1998-08-01), Roh et al.
patent: 5852581 (1998-12-01), Beffa et al.
patent: 5936899 (1999-08-01), Jeong
patent: 6026038 (2000-02-01), Cho et al.
patent: 6037792 (2000-03-01), McClure
Tohru et al., Wafer Burn In (WBI) Technology for RAM's, IEEE, p. 639-642, 1993.
Chien Pien
Lee Jin-Yuan
Ackerman Stephen B.
Chase Shelly A
De'cady Albert
Saile George O.
Taiwan Semiconductor Manufacturing Company
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