VRAM-based parity engine for use in disk array controller

Details VRAM-based parity engine for use in disk array controller VRAM-based parity engine for use in disk array controller

1997-05-30

1999-10-12

Butler, Dennis M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

711100, G06F 1300

Patent

active

059648953

ABSTRACT:
A VRAM-based parity engine for use in a disk array controller is disclosed, in which the parity arithmetic operation is carried out in a fast and effective manner, thereby improving the performance of the RAID system. Particularly, the parity data arithmetic operation is not resorted to a processor, but to a VRAM, thereby realizing a high speed operation. In the disk array controller, a VRAM (video RAM) is used, in such a manner that the reading, updating and writing are made to be overlapped during the arithmetic operation, thereby promoting the speed of the arithmetic. Therefore, a relatively large capacity memory can be formed compared with the conventional SRAM, and therefore, a temporary buffer memory within the parity engine is used as a parity cache, thereby doubling the performance.

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A Case for Redundant Arrays of Inexpensive Disks (RAID), David A. Patterson, Garth Gibson and Randy H. Katz, (Patterson et al., ACM SIGMOD Conference, Chicago, II Jun. 1-3, 1988, pp. 109-116).

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