VPX bank architecture

Details VPX bank architecture VPX bank architecture

2001-08-07

2002-10-08

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S185110, C365S230060

Reexamination Certificate

active

06463004

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of computers and computer systems. More particularly, the present invention relates to a method and apparatus for a VPX bank architecture.
BACKGROUND OF THE INVENTION
Many of today's computing applications such as cellular phones, digital cameras, and personal computers, use nonvolatile memories to store data or code. Non-volatility is advantageous because it allows the computing system to retain its data and code even when power is removed from the computing system. Thus if the system is turned off or if there is a power failure, there is no loss of code or data. Such nonvolatile memories include Read-Only Memory (ROMs), Electrically Programmable Read-Only Memory (EPROMs), Electrically Erasable Programmable Read-Only Memory (EEPROMs), and flash Electrically Erasable Programmable Read-Only Memory (flash EEPROMs or flash memory).
Nonvolatile semiconductor memory devices are fundamental building blocks in computer system designs. One such nonvolatile memory device is flash memory. Flash memory can be programmed by the user, and once programmed, the flash memory retains its data until the memory is erased. Electrical erasure of the flash memory erases the contents of the memory of the device in one relatively rapid operation. The flash memory may then be programmed with new code or data. The primary mechanism by which data is stored in flash memory is a flash memory cell. Accordingly, outputs of a flash memory device are typically associated with an array of flash cells that is arranged into rows and columns such that each flash cell in the array is uniquely addressable.
A flash EEPROM memory device (cell) is a floating gate MOS field effect transistor having a drain region, a source region, a floating gate, and a control gate. Conductors are connected to each drain, source, and control gate for applying signals to the transistor. A flash EEPROM cell is capable of functioning in the manner of a normal EPROM cell and will retain a programmed value when power is removed from the circuitry. A flash EEPROM cell may typically be used to store a one or zero condition. If multilevel cell (MLC) technology is used, multiple bits of data may be stored in each flash EEPROM cell. Unlike a typical EPROM cell, a flash EEPROM cell is electrically erasable in place and does not need to be removed and diffused with ultraviolet to accomplish erasure of the memory cells.
Arrays of such flash EEPROM memory cells have been used in computers and similar circuitry as both read only memory and as long term storage which may be both read and written. These cells require accurate values of voltage be furnished in order to accomplish programming and reading of the devices. Arrays of flash EEPROM memory devices are typically used for long term storage in portable computers where their lightweight and rapid programming ability offer distinct advantages offer electro-mechanical hard disk drives. However, the tendency has been to reduce the power requirements of such portable computers to make the computers lighter and to increase the length of use between recharging. This has required that the voltage potentials available to program the flash memory arrays be reduced.
FIG. 1
is a typical prior art memory architecture
100
. A charge pump
102
provides a pumped voltage potential
104
. Pump voltage
104
is supplied to X-path switches
106
. Logic circuits of the X-path switches
106
control the voltage potentials coupled to the X-path during read, write, and erase modes in the memory. The outputs of the X-path switches
106
are coupled to X-decoders
112
,
122
. Each supply voltage from the switched outputs
108
from the X-path switches
106
have to supply all the X-decoder devices
112
,
122
in both planes
110
,
120
.
The embodiment in
FIG. 1
has a memory array divided into two planes
110
,
120
. The first plane
110
and second plane
120
are similar in construction. Global wordlines
114
,
124
from the X-decoders
112
,
122
are coupled to local block selects
116
,
126
in each block of the memory block in the corresponding planes
110
,
120
. The local block selects
116
,
126
determine whether the global wordlines
114
,
124
are coupled to the local wordlines
118
,
128
in a block.
The X-path switches of prior art designs provided a single set of high voltages signals that are coupled to circuits for the entire memory array. A high voltage signal can be coupled to devices on both planes of memory. In other words, whenever each high voltage signal transitioned from one voltage to a higher voltage potential, that high voltage signal needed to supply current to all the circuit devices coupled to its signal. Hence, each high voltage signal has to charge up a large amount of capacitance, which increases the current and power consumption.
A number of the electronic systems that use flash memories are small portable devices that rely on batteries for power. As new applications emerge, system designers are open to alternative methods of increasing the battery life of these devices by reducing power consumption.
SUMMARY OF THE INVENTION
A method for a VPX banked architecture is described. The method comprises of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follow below.


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patent: 4878203 (1989-10-01), Arakawa
patent: 5886939 (1999-03-01), Choi
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patent: 5978277 (1999-11-01), Hsu et al.
patent: 6023427 (2000-02-01), Lakhani et al.
patent: 6038169 (2000-03-01), Ogura
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patent: 6091659 (2000-07-01), Watanabe et al.
patent: 6115316 (2000-09-01), Mori et al.

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