Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-02-23
2002-10-15
Zarabian, A. (Department: 3721)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230060, C327S170000
Reexamination Certificate
active
06466485
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention is directed to memory devices generally and, more particularly, to voltage regulators and data paths used in such devices.
2. Description of the Background
Solid state memory devices communicate with the outside world through input/output pads. Some pads may be connected to an address bus and are thus dedicated to receiving address information. Other pads may be connected to a command bus from which command signals are received while still other pads are connected to a data bus, on which data to be written into the memory is received or data read from the memory is output. In other types of devices, the pads may be connected to a single multiplexed bus which, at one point in time outputs address and command information and, at another point in time, outputs or receives data.
To enable pads to receive or send information, the information is transmitted in the form of ones and zeros. The “ones” and “zeros” are typically represented by two different voltage levels. For example, a voltage between two and five and one half volts may be considered to represent a high signal, or a “one”, while a voltage level of between minus 0.3 volts and plus 0.8 volts may be considered to represent a low signal, or a “zero”. The output pads must be capable of reliably producing voltages within the ranges designated as representing ones and zeroes in accordance with timing specifications set for the component.
Timing specifications are typically set by the consumers of the memory devices for particular applications. A timing specification would identify how long it may take for an output pad to change from a zero to a one, e.g. change from minus 0.3 volts to plus five volts, how abrupt the changes must be, etc. With access times for memory devices measured in nanoseconds, it is clear the design engineer is faced with quite a challenge to design electrical circuits which can change the voltage available at the output pads so quickly.
Output pads typically are serviced by a number of circuits such as circuits for buffering (holding) data, and drive circuits for driving the voltage on the pad to a voltage representative of data to be output. The drive circuit, in turn, is serviced by devices such as voltage generators and voltage regulators which provide the power needed by the output pad drivers. The voltage regulator is used to provide power, in the form of voltage for driving the gate of an output transistor ultimately servicing an output pad. Typically, voltage regulators supply that gate voltage (Vgate) to a number of drive transistors through a voltage bus.
When the gate voltage is heavily loaded, the Vgate level recovery may not be sufficiently quick. Prior art attempts at solving this problem apply a one-shot pulse to an enable Vgate line. However, because the path between Vgate and the enable Vgate line is through a p-channel transistor with its n-well biased to Vgate, there is a risk of forward biasing the drain of the p-channel to the n-well if the one-shot pulling the enable V-gate line towards system voltage (V
DD
) is not timed properly across all process and device conditions. Additionally, if the one-shot timing is too weak under particular process and device conditions, then Vgate will droop, and the enable Vgate lines will not recover sufficiently quickly.
Another problem is experienced in the prior art when the memory device, and hence the voltage regulator, must go into a nap or a standby mode. In such modes, the Vgate regulator needs to go to a low power mode very quickly. In some prior art configurations, that is accomplished by reducing the bias voltage supplied to an amplifier within the voltage regulator. However, simply reducing the bias voltage may not reduce the power consumption of the voltage regulator sufficiently quickly.
Another problem is encountered because output transistors typically have an RC time constant associated therewith as a result of their loading. The RC time constant prevents the output transistor from reducing its drive sufficiently quickly. In the prior art, a pass gate is used to disconnect the RC so that the output transistor can respond more quickly. However, that approach leaves one side of the RC load floating. Due to n-plus junctions, the floating side can move to a back bias voltage. Should that occur, when the RC is reconnected to the transistor, the transistor would be turned on hard.
Other problems associated with the data path relate to the output slew of data pad drivers. In the prior art, output slew rates are improved by segmenting the output transistors into two main portions and delaying the switching of one of the portions. The delay is controlled by a circuit that makes a determination as to the strength of the p- and n-channel transistors and generates a two-bit binary code. In addition to setting the delay based on the two-bit code, a NAND gate is used to receive the two-bit signal which, in turn, enables a p-channel transistor to further enable two other p-channel transistors in the output pre-driver so that they could strengthen the high side out of the pre-driver for both the normal and delayed paths. However, various changes over process and device conditions can cause the output's timing characteristic to be skewed. Because the prior art solution enables only the addition of p-channel transistors in one of the two-bit code cases, the degrees of freedom to compensate for various types of skew are limited.
Thus, the need exists for a voltage regulator and data path with improved performance characteristics.
SUMMARY OF THE PRESENT INVENTION
One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator.
Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator having its output terminal connected to a voltage bus, and with the voltage bus serving a plurality of output blocks through a plurality of output lines. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration. A plurality of delay circuits receives the control pulse and produces a plurality of delayed control pulses. A second logic gate receives the control pulse and the plurality of delayed control pulses and produces a control pulse of extended duration. The control pulse of extended duration may be used, for example, for temporarily sourcing additional current to an output terminal of the voltage regulator.
According to another aspect of the present invention, a method is disclosed of forcing a voltage regulator into a low power mode. The method involves increasing the rate at which a bias voltage is withdrawn from an amplifier in the voltage regulator. A node between a resistive and capacitive load connected to an output transistor of the voltage regulator is pulled to a predetermined voltage other than ground. By reducing the bias voltage, power consumption is rapidly diminished. Furthermore, by pulling the node to a predetermined voltage other than ground, the node is prevented from floating to a voltage which will turn the transistor on hard when reconnected.
Another aspect of the present invention is directed to a pre-driver or the like which provides variable output drive capability. The pre-driver is comprised of two paths each divided into output stages. A two-bit signal is generated in response to determining the relative strength of the n-channel and p-channel transistors in a subsequent output a
Thorp Reed & Armstrong LLP
Zarabian A.
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