Voltage-level shifter and semiconductor memory using the same

Details Voltage-level shifter and semiconductor memory using the same Voltage-level shifter and semiconductor memory using the same

2002-07-02

2003-01-21

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189090

Reexamination Certificate

active

06510089

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35USC § 119 to Japanese Patent Application No. 1999-342573 filed on Dec. 1, 1999 in Japan, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
The present invention relates to a signal voltage-level shifter and a semiconductor memory using the shifter.
Several electrically-erasable non-volatile semiconductor memories (EEPROM) have been known. Each memory cell of EEPROMs is constituted by a MOS transistor having stacked floating and control gates. A memory cell array can be formed by connecting a plurality of memory cells in NOR- or NAND-type. Both types of memory cell array require several internal boosted high voltages and negative voltages according to operation mode, such as, data programming and erasing.
A NOR-type EEPROM operates as follows: Voltages at 5V and 9V are applied to the drain and the control gate, respectively, of a selected memory cell while the source is grounded, for data programming. This voltage application allows hot electrons to be injected into the floating gate to shift a threshold level of the selected memory cell toward a positive level, which is a programmed state, such as, a “0”-state.
Data programming includes a data verification operation to verify that data has been programmed. The verification operation applies a voltage, such as, 6.5V, to the control gate, that is higher than that for a regular data reading operation to judge whether the programmed data is “0” or not. Data programming is performed again if programming is insufficient.
Concerning data erasing, all data are usually erased for each unit of block. Voltages at −7V and 5V are applied to the control gate and the common source, respectively, while the drain is floating in each memory cell in a selected block.
This voltage application allows electrons in the floating gate to be discharged to the source with a tunnel current to shift a threshold level of the selected memory cell toward a negative level, which is an erased state, such as “1”-state. The same can be done by applying, for example, 10V to the source and well regions, electrons being discharged from the entire channel region with a tunnel current.
Data erasing also includes a data verification operation to verify that data has been erased. The verification operation applied a voltage, such as, 4V, to the control gate, that is lower than that for a regular data reading operation to judge whether the memory cell in the erased block is “1” or not. Data erasing is performed again if insufficient.
Over-erasing occurs to memory cells that are easily erased among blocks to be erased. An over-erased memory cell, having a negative threshold level at which a current flows even at 0V to the control gate, obstructs a regular reading operation due to a leakage from a non-selected cell when 0V and a voltage for reading are applied to the control gates of the non-selected cell and a selected cell in a “0”-state, respectively, thus resulting in erroneous reading of a “1”-state from the “0”-state selected cell.
A weak programming is performed to ease an over-erased state or an over-erased memory cell. One technique is to apply 0V and 5V to the control gate and the corresponding bit line, respectively, to set memory cells connected to the bit line to meet a weak programming requirement. This technique utilizes potential rising at the floating gate due to capacitance-coupling from the drain, which is called a self-convergence technique due to that fact that electrons injected into the floating gate decrease its potential so that the programming requirement is not met.
Another technique to ease an over-erased state of an over-erased memory cell is to apply 3V and 5V to the control gate and the drain, respectively, to set selected memory cells to meet a weak programming requirement. This voltage application allows hot electrons to be injected into the floating of an over-erased memory cell to ease the over-erased state. This technique requires a voltage of, for example, −1.5V, to the control gate of non-selected cells for non-selected over-erased cells not to be turned on.
FIG. 1
represents Vgs-to-Ids characteristics for several states of EEPROM as described above.
A normally programmed state “0” and a normally erased state “1” are represented by OFF and ON, respectively, for a voltage Vread for reading applied to the control gate. An over-erased state is a state in which electrons have been discharged until the threshold level becomes negative. Self convergence state (
1
) and weak program state (
2
) represent a weak programming and an active programming, respectively, under the self-convergence technique.
As discussed, EEPROMs use variety of voltages according to operation modes. EEPROMs have a chip-in-voltage booster for generating several high voltages and also a chip-in-voltage-level shifter in an address decoder for shifting VCC-VSS amplitude signal voltage to control voltages of several levels.
For example, as shown in a well-known circuit in
FIG. 2
, a first voltage-level shifter
2
and a second voltage-level shifter
3
are connected to the output of a row decoder
1
for selectively activating word lines.
The row decoder
1
performs an identification operation to addresses A
0
, A
1
, . . . , to output complimentary decode output signals “a” and “b” having an amplitude of VCC-VSS.
The signals “a” and “b” are supplied to the first voltage-level shifter
2
and converted into signals “A” and “B”, respectively, having a potential VSW higher than the high level of the corresponding signal “a” or “b”. The potential VSW is a high potential for programming and supplied by a voltage booster (not shown), which will become a potential Vread in reading.
The signals “A” and “B” are supplied to the second voltage-level shifter
3
and converted into signals “OUTA” and “OUTB”, respectively, having a potential VBB lower than the low level of the corresponding signal “A” or “B”. At least either the signal “OUTA” or “OUTB” is supplied to a word line driver (not shown).
The first voltage-level shifter
2
consists of NMOS transistors QN
1
and QN
2
provided at the VSS-side, that receive the signals “a” and “b”, respectively, and PMOS transistors QP
1
and QP
2
provided at the VSW-side. The transistors QP
1
and QP
2
constitute a flip-flop in which the gate and drains are cross-connected for positive feed-back to shift the high-level potential of the signals “a” and “b” from VCC to VSW.
The second voltage-level shifter
3
consists of PMOS transistors QP
3
and QP
4
provided at the high-level VSW-side, that receive the signals “A” and “B”, respectively, and NMOS transistors QN
3
and QN
4
provided at the low-level VBB-side. The transistors QN
3
and QN
42
constitute a flip-flop in which the gate and drains are cross-connected to shift the low-level potential “A” and “B” from VSS to VBB.
The voltage-level shifters
2
and
3
are, however, are disadvantageous for an unstable switching operation in voltage-level shifting.
This disadvantage is discussed in detail with respect to the second voltage-level shifter
3
for low-level side shifting.
FIG. 3
represents voltage-to-current characteristics of the PMOS transistor QP
3
and the NMOS transistor QN
3
. The curve C
1
represents a static characteristic when a gate voltage Vg supplied to the NMOS transistors QN
3
is VSW. The curve C
2
is a load characteristic curve given by the PMOS transistor QP
3
the conductance of which is controlled by the input signal “A”.
The signs I
1
and I
2
represent a current at a voltage 0V (“A”=VSS) to the PMOS transistor QP
3
on the load characteristic curve C
2
and a current at a voltage 0V to the NMOS transistor QN
3
on the static characteristic C
1
, respectively.
A normal voltage-level shifting for the second voltage-level shifter
3
must meet the requirement I
1
>I
2
. If I
1
≦I
2
, the transistors QP
3
and QP
4
are tuned off and on, respectively, thus the transistors QN
3
and QN
4
are tuned

Affiliated with

Also associated with

Rating

Voltage-level shifter and semiconductor memory using the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage-level shifter and semiconductor memory using the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage-level shifter and semiconductor memory using the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3059168