Voltage level converting buffer circuit

Electronic digital logic circuitry – Interface – Logic level shifting

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Details

326121, H03K 190944

Patent

active

053789458

ABSTRACT:
A voltage level conversion buffer circuit including a first and a second transistor each having a gate, a drain, and a source. The drain of the first transistor and the gate of the second transistor are connected together to provide an input to the buffer circuit, and the gate of the first transistor and the drain of the second transistor are connected to a supply voltage. The sources of the first and second transistors are connected together to provide an output for the buffer circuit.

REFERENCES:
patent: 4935649 (1990-06-01), Bloker
patent: 4963765 (1990-10-01), Kadakia et al.
patent: 5057712 (1991-10-01), Trinh et al.
patent: 5151616 (1992-09-01), Komuro

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