Voltage compensating CMOS input buffer circuit

Details Voltage compensating CMOS input buffer circuit Voltage compensating CMOS input buffer circuit

1995-08-23

1996-11-26

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 33, 326 70, 326 83, H03K 190185, H03K 190948

Patent

active

055789412

ABSTRACT:
A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points. An output stage inverter provides the CMOS logic levels from the output of the input inverter.

REFERENCES:
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patent: 4988897 (1991-01-01), Jeong
patent: 5128560 (1992-07-01), Chern et al.
patent: 5278460 (1994-01-01), Casper
patent: 5408191 (1995-04-01), Han et al.
patent: 5416366 (1995-05-01), Adachi
patent: 5438280 (1995-08-01), Sugawara

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