Viterbi decoder architecture for use in software-defined...

Details Viterbi decoder architecture for use in software-defined... Viterbi decoder architecture for use in software-defined...

2005-12-21

2009-10-13

Baderman, Scott T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S792000, C714S799000

Reexamination Certificate

active

07603613

ABSTRACT:
A reconfigurable Viterbi decoder comprising a reconfigurable data path and a programmable finite state machine that controls the reconfigurable data path. The reconfigurable data path comprises a plurality of reconfigurable functional blocks including: i) a reconfigurable branch metric calculation block; and ii) a reconfigurable add-compare-select and path metric calculation block. The programmable finite state machine executes a plurality of context-related instructions associated with the reconfigurable Viterbi decoder.

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