Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-23
2004-02-24
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S697000, C438S626000
Reexamination Certificate
active
06696358
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to the planarization of surfaces during the fabrication of integrated circuits and to viscous protective overlayers retarding etching of depressed surface regions. More particularly, the present invention relates to the planarization of copper surfaces and tantalum/tantalum nitride barrier layers, and to the use of viscous overlayers facilitating planarization and mitigating dishing that typically occurs in the planarization of large copper damascene and dual damascene features.
2. Description of Related Art
Increasing the performance of integrated circuits (“ICs”) typically calls for increasing the density of components on the wafer and increasing the speed at which the IC performs its functions. Increasing component density typically requires decreasing the size of the conducting trenches and vias (“interconnects”) on the wafer. However, decreasing the cross-section of a current-carrying conductor increases the electrical resistance for the same conducting material, degrading circuit performance and increasing the heating of the interconnects. Present IC technology typically makes use of tungsten (W) and aluminum (Al) interconnects and/or alloys containing these materials. Both metals, Al and W, and typical alloys thereof have adequate electrical conductivity for use in present devices, but future generations of ICs will preferably make use of higher conductivity materials. Copper (Cu) is among the leading candidates.
While Cu has the advantage of higher conductivity than current IC interconnect materials, it suffers from several disadvantages. Cu is a very diffusive contaminant, diffusing easily and widely through other materials typically used in the fabrication of ICs, seriously degrading IC performance in so doing. Tantalum (Ta) and tantalum nitride (TaN) have been identified as promising barrier materials or “liners” that may be deposited prior to Cu deposition, thereby hindering the diffusion of Cu into the surrounding material. A recent review of copper IC interconnect and other microelectronic technology is given by Shyam P. Murarka, Igor V. Verner and Ronald J. Gutmann in
Copper—Fundamental Mechanisms for Microelectronic Applications,
(John Wiley, 2000).
Planarization is a necessary step in the fabrication of multilayer ICs, providing a flat, smooth surface that can be patterned and etched with the accuracy required of modern IC components. The conventional planarization technique is CMP (Chemical Mechanical Planarization) known in the art and described in text books (for example,
Chemical Mechanical Planarization of Microelectronic Materials,
by Joseph M. Steigerwald, Shyam P. Murarka and Ronald J. Gutman, 1997). CMP makes use of a polishing pad brought into mechanical contact with the wafer to be planarized with an abrasive slurry interposed between polishing pad and wafer. Relative motion (typically rotation) of the polishing pad with respect to the wafer leads to polishing of the wafer through mechanical abrasion and chemical etching caused by suitable reactive chemicals contained in the etching solution. Non-contact planarization has also been proposed in which effectively no mechanical abrasion occurs on the wafer, planarizing by means of chemical effects. One such non-contact planarization techniques makes use of a spinning wafer and suitable etching chemicals (“spin-etch planarization”) and is described in application Ser. No. 09/356,487 (incorporated herein by reference). Some aspects of non-contact planarization have been reported by J. Levert, S. Mukherjee and D. DeBear “Spin-Etch Planarization Process for Copper Damascene Interconnects” in
Proceedings of SEMI Technology Symposium
99, Dec. 1-3, 1999, pp. 4-73 to 4-82. See also J. Levert, S. Mukherjee, D. DeBear and M. Fury “A Novel Spin-Etch Planarization Process for Dual-Damascene Copper Interconnects” in
Electrochemical Society Conference, October
1999, p. 162 ff. And see also, Shyama P. Mukherjee, Joseph A. Levert and Donald S. DeBear, “Planarization of Copper Damascene Interconnects by Spin-Etch Process: A Chemical Approach,” MRS Spring Meeting, San Francisco, Calif., Apr. 27, 2000 including the references cited in all of the foregoing.
Other copper planarization procedures include that of Moslehi (WO 99/14800) and electrochemical or electropolishing techniques described by Cantolini and co-workers (J. Electrochem. Soc. Vol. 141, No. 9, pp. 2503-2510, September 1994 and WO 92/07118).
The present invention relates to improved methods for the planarization of Cu/Ta/TaN layers in the fabrication of ICs. The present invention may be employed in connection with spin-etch planarization, conventional CMP or other planarization techniques that are apparent to those having ordinary skills in the art.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. To be definite in our discussion, we consider an example of considerable current technological interest, the planarization of copper surfaces and Ta/TaN barrier layers. Application of the invention disclosed herein to the planarization of other systems will be apparent to those having ordinary skills in the art.
Following deposition of the copper layer, surface topography in the upper surface of copper layer is to be removed by the planarization process, resulting in a substantially planar conductor co-planar with the surrounding dielectric. “Dishing” relates to the tendency to form a concave region in the copper interconnect lying below the plane of the dielectric surface. Dishing is a problem typically most pronounced in the planarization of large interconnects.
The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. Simultaneously, the raised less-protected regions of surface topography are preferentially removed. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions, thereby hindering the dissolution of interconnect copper into the protective overlayer. Other species inhibiting or passivating the copper surface from dissolution may be included in the viscous overlayer, including quinolines or benzotriazol among others. In some embodiments of the present invention, the viscous overlayer may be added prior to the introduction of etchant to the wafer surface, or both etchant and viscous overlayer may be introduced substantially simultaneously, typically as the wafer is spun during planarization. One embodiment relates to a method of planarizing a metal surface in the fabrication of integrated circuit interconnects comprising introducing a protecting fluid onto said metal surface and dispersing said protecting fluid across said metal surface and introducing an etching solution onto said metal surface, whereby the viscosity of said protecting fluid exceeds that of said etching solution thereby hindering etching of said surface in regions of said surface occupied by said protecting layer and etching said metal surface to planarity.
REFERENCES:
patent: 5173130 (1992-12-01), Kinoshita et al.
patent: 6146991 (2000-11-01), Cheng et al.
patent: 6280644 (2001-08-01), Martin et al.
J. Levert, S. Mukherjee, D. DeBear, and M. Fury entitled, “A Novel Spin-Etch Planarization Process for Dual-Damascene Copper Interconnects”, Oct. 19, 1999, 12 Pages.
J. Levert, S. Mukherjee, D. DeBear entitled, “SEMI Technology Symposium 99 Proceedings”, Dec. 1999, 10 Pages.
Debear Donald
Levert Joseph
Mukherjee Shyama
Bingham McCutchen
Fahmy Wael
Honeywell International , Inc.
Thompson Sandra P.
Trinh Hoa B.
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