Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-02-14
2006-02-14
Elmore, Stephen C. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S112000, C711S111000, C711S162000, C700S082000, C707S793000, C714S006130
Reexamination Certificate
active
07000086
ABSTRACT:
Ordering data writes include a host computer providing a plurality of data writes to a primary storage device, the primary storage device assigning a first sequence number to data writes begun after a first time and before a second time, the primary storage device assigning a second sequence number, different from the first sequence number, to data writes begun after the second time, in response to completion of all writes assigned the first sequence number, the primary storage device transferring writes assigned the first sequence number to a secondary storage device, and, in response to the primary storage device transferring all writes assigned the first sequence number to the secondary storage device, the primary storage device sending a commit message to the secondary storage device. Ordering data writes may also include, in response to receiving a commit message from the primary storage device, the secondary storage device storing the data writes having the first sequence number.
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Halstead Mark J.
Kopylovitz Haim
Meiri David
Moreshet Hana
Ofer Adi
Elmore Stephen C.
EMC Corporation
Muirhead and Saturnelli LLC
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