Virtual ground silicide bit line process for floating gate...

Details Virtual ground silicide bit line process for floating gate... Virtual ground silicide bit line process for floating gate...

2002-09-10

2004-04-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S260000, C257S315000, C257S316000, C257S321000, C257S322000, C365S185040, C365S189011, C365S222000

Reexamination Certificate

active

06716698

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and more particularly to flash memory devices.
BACKGROUND OF THE INVENTION
There has long been a demand for small, portable personal devices. These devices include cellular phones, personal computing equipment, and personal sound systems, which are sought in continuously smaller sizes and with continuously lower power requirements. At the same time that smaller and more portable devices are sought, computational power and on-chip memory requirements are increasing. In light of these requirements, there has been a long-felt need for computational devices that have substantial memory and logic functions integrated within individual semiconductor chips. Preferably, the memory is configured such that if power is interrupted, as when a battery fails, the contents of the memory are retained. Memory that retains its content without a continuous supply of power is called non-volatile memory. Non-volatile memory types include, for example, electrically erasable, programmable read only memory (EEPPROM) and flash EEPROM.
The term “flash” refers to the ability of the memory to be erased in blocks. Flash memory devices typically store electrical charges, representing data, in transistors having either a floating-gate or a charge-trapping dielectric. The stored charges affect the threshold voltage of the transistors. For example, in an n-channel floating-gate transistor an accumulation of electrons in the floating-gate electrode creates a high threshold voltage in the transistor. The presence or absence of the stored charge can be determined by whether current flows between a source region and a drain region of the transistor when appropriate voltages are applied to the control gate, source, and drain.
Various structures have been proposed for making flash memory devices. Prior art
FIG. 1
illustrates a conventional NOR configuration
10
, wherein the control gate
11
is connected to a word line (e.g., WL
0
thru WL
3
) associated with a row of such cells
12
to form sectors of such cells. In addition, the drain regions
13
of the cells are connected together by a conductive bit line (e.g., BL
0
thru BL
3
). The channel of the cell conducts current between the source
14
and the drain
13
in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal
13
of the transistors
12
within a single column is connected to the same bit line. In addition, each flash cell
12
associated with a given bit line has its stacked gate terminal
11
coupled to a different word line (e.g., WL
1
thru WL
4
), while all the flash cells in the array have their source terminals
14
coupled to a common source terminal (CS). In operation, individual flash cells
12
are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
In addition to the NOR configuration, some prior art flash memories use a “virtual ground” architecture, as shown in
FIG. 2. A
typical virtual ground architecture
20
comprises rows
24
of flash cells
21
with its stacked gate terminal
30
coupled to an associated word line (e.g., WL
0
thru WL
n
)
24
, and columns (
26
,
27
,
28
,
29
) of flash cell pairs (
21
&
23
) with a drain
32
of one transistor
23
coupled to an associated bit line (e.g., BL
0
thru BL
m
) and the source
22
of the adjacent transistor
21
coupled to the same bit line
27
. In addition, each single row of flash cells (e.g.,
21
&
23
) associated with a word line
24
is connected in series, with the source
22
of one cell
21
coupled to the drain
32
of an adjacent cell
23
, wherein each drain terminal of the transistors within a single column is connected to the same bit line.
An individual flash cell is selected via the word line and a pair of bit lines bounding the associated cell. For example, in reading the flash cell
21
, a conduction path would be established when a positive voltage is applied to the bit line (BL
0
)
26
coupled to the drain of flash cell
21
, and the source
22
which is coupled to the bit line (BL
1
)
27
, is selectively coupled to ground (V
SS
). Thus, a virtual ground is formed by selectively switching to ground the bit line associated with the source terminal of only those selected flash cells which are to be programmed or read.
As can be seen from the above, while a non-virtual ground array structure has dedicated source and drain regions for reading and writing operations, a virtual ground array structure reduces the spacing between cells by employing dual purpose bit lines that can serve as either sources or drains according to the voltages applied.
Myriad approaches have been proposed for making flash memory devices more compact. These approaches include improved processing techniques to produce smaller cells, improved materials that lend themselves to smaller cell sizes, and improved architectures that use space more efficiently. Nonetheless, there remains a long felt need for more compact flash memory devices.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some of its aspects. This summary is not an extensive overview of the invention and is intended neither to identify key or critical elements of the invention nor to delineate its scope. The primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to a virtual ground array floating gate flash memory device with salicided buried bit lines. The bit lines are implanted and salicided after formation of memory cell stacks, but before formation of word lines that connect memory cell control gates. Saliciding bit lines enables the use of narrower bit lines, fewer bit line contacts, and a shallower source/drain implant, all of which facilitate the formation of compact memory. Saliciding memory cell control gates facilitates contact with word lines.
According to another aspect of the invention, the control gate layer is relatively thin, for example, no more than about 500 Angstroms. Having a thin control gate layer improves the aspect ratio for the etch that defines the bit lines and facilitate the formation of compact memory.
A further aspect of the invention relates to a process for forming virtual ground array floating gate flash memory devices in which the floating gates are patterned prior to depositing an interpoly dielectric. In this process, the interpoly dielectric coats the sides of the floating gates and significantly improves the capacitance between the floating gates and the memory cell channels.


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