Virtual ground flash cell with asymmetrically placed source and

Details Virtual ground flash cell with asymmetrically placed source and Virtual ground flash cell with asymmetrically placed source and

1997-01-15

1998-11-17

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438286, H01L 218247

Patent

active

058375848

ABSTRACT:
A memory cell having asymmetrically placed source and drain diffusions which allows programming and erasure to be obtained across one of the source or drain diffusions which extends furthest beneath the floating gate while minimizing electron tunneling at the other of the source or drain diffusions which extends only minimally beneath the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a first and second column of floating gate cores on the dielectric; (3) implanting a first dopant adjacent the second column and displaced from the first column, the first dopant having a second conductivity type opposite the first conductivity type; (4) forming floating gate sidewalls in contact with the floating gate cores; (5) implanting a second dopant between the floating gate sidewalls, the second dopant having the second conductivity type; (6) forming a thermal oxide between the first and second column of floating gate cores such that oxide encroachments are formed below the floating gate cores of the first and second column and the first dopant is separated from the second column of floating gate cores by the first dielectric and the second dopant is separated from first column of the floating gate cores by the oxide encroachment; and (7) completing formation of control gate dielectric and control gates. The presence of tunneling and non-tunneling connections on the source and drain side of each cell improves the isolation between adjacent memory cells and minimizes the disturb problem.

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Noriyuki, S., "Semiconductor Memory Device and Drive System Therefor", Patent Abstracts of Japan, vol. 018, No. 545, Publ. No. 06196713, 15 Jul. 1994.
Ohi, M. et al., "An Asymmetrical Offset Source/Drain Structure for Virtual Ground Array Flash Memory with DINOR Operation", Digest of Technical Papers of the Symposium on VLSI Technology, Kyoto, May 17-19, 1993, IEEE, pp. 57-58.
Yamauchi, Y. et al., "A New Cell Structure for Sub-quarter Micron High Density Flash Memory", Technical Digest of the International Electron Devices Meeting, Washington, Dec. 10-13, 1995, IEEE, pp. 267-270.

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