Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
1999-07-14
2001-09-11
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C712S226000, C712S209000
Reexamination Certificate
active
06289440
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Disclosure of the Co-Pending Application
The above-referenced co-pending parent application discloses a virtual computer consisting of a reconfigurable control section and a reconfigurable computation array. Preferably, the reconfigurable control section is a relatively small array of interconnected field programmable gate arrays (FPGAs), while the reconfigurable computation array is a relatively large array of interconnected FPGAs whose configurations are governed by the control section. When power is first turned on, the control section automatically configures itself to emulate a microprocessor suitable for rapidly re-configuring the computation array in response to each new instruction to be carried out or executed. (The term “instruction” as understood herein is generic and can refer to either an individual instruction of a program, a group of instructions, an algorithm, a sub-routine or a program.) Preferably, the control section compiles each new instruction (e.g., an individual instruction of a program, a group of instructions, an algorithm, a sub-routine or a program) by generating therefrom respective sets of configuration bits for respective ones of the FPGAs in the computation array, and then causing those computation array FPGAs to be reconfigured accordingly. The advantage is that such a virtual computer has far greater speed than a conventional computer, as explained more fully in the above-referenced application. While the above-referenced application discloses an implementation employing many FPGAs in both the computation array and in the control section, other implementations may be carried out using a smaller number of FPGAs. For example, a limited application could suffice with only a single FPGA in the control section and a single FPGA in the computation array.
2. Background Art
Computer networks of the type usually referred to as “local area networks” or LANs are well-known in the art, one of the best known LANs being the Ethernet™ LAN. Such networks have many uses such as, for example, permitting instant communication among co-workers at respective terminals or nodes of the network. Each terminal or node may be a personal computer or a work station. Another use of an LAN is to emulate a supercomputer by joining many work stations over an LAN. A fundamental problem with such a network is that the node or terminal (a personal computer, work station or the like) must act as a host and perform a number of required tasks, which necessarily consumes the resources of the host, or postpones such tasks while the host completes higher-priority tasks. The required tasks can include performing the network protocol tasks, converting data on the network (typically serial error correction encoded compressed data blocks) into parallel 16-bit words for processing in the host, and vice-versa, decoding data packet headers, and so forth. Because of the demand on-the host's limited processing resources, these tasks are necessarily performed at a limited speed, so that the rate at which data can be communicated over the LAN is limited. Moreover, from the point of view of the host's user, participation in the network requires some sacrifice of the host's resources to network-related tasks.
SUMMARY OF THE INVENTION
The invention is embodied in a virtual network consisting of many distributed virtual computers interconnected over a communication network of individual links, such as optical fibers or electrical conductors, for example. Each distributed virtual computer has at least two ports connected over respective links to other respective distributed virtual computers on the network. Each distributed virtual computer is connected to or resident within its own host, each host typically being a conventional computer such as a personal computer or a work station, for example, although at least one of the hosts may itself be another virtual computer. Each distributed virtual computer has reconfigurable logic elements such as an FPGA or an array of FPGAs. At power-up, at least one of the FPGAs in at least one of the distributed virtual computers is automatically configured (e.g., from instructions stored in a non-volatile read-only memory or from instructions from a host) into a microprocessor-like device which then configures one or some “control” FPGAs or “control” portions of single FPGAs in the various distributed virtual computers to give them control or “compiling” capability over the remaining FPGA resources, which act as a computation FPGA array. Such control or compiling capability means that the “control” FPGA (or the “control” portion of a single FPGA) so configured can react to instructions received from a host or from other nodes on the network to re-configure FPGA elements in the computation array to carry out a required task. Thus, the control FPGA (or FPGAs) in the distributed virtual computer can function in the manner of the control section of the virtual computer described in the above-referenced co-pending application to compile received instructions or algorithms into configuration bit files and reconfigure the computation array FPGA elements in accordance with the configuration bit files to optimally carry out each instruction or algorithm. Alternatively, the host computer can assume some of the re-configuring or compiling tasks. Such a network of distributed virtual computers is referred to herein as a virtual network.
In one embodiment, each host is connected to a node of a conventional LAN as well as being connected to a distributed virtual computer or node of the virtual network, so that there are two networks interconnecting the same set of host computers.
Each distributed virtual computer can be configured to perform all of the network node tasks for the virtual network, which are the same type of tasks discussed above concerning the conventional network or LAN, including decompression, decoding and so forth. Thus, the virtual computer network does not consume the resources of the host computer for such tasks, a significant advantage over conventional networks. Another advantage is that the FPGAs of the distributed virtual computers can be optimally configured to perform specific difficult tasks at extremely high speeds, such as translation of packet headers at gigabit rates, something a conventional computer is generally incapable of doing.
Since each distributed virtual computer can be reconfigured at any time for specific tasks, the virtual network can rapidly transition between various operating modes as needed. For example, in one mode at least some of the host computers of the network can be slaved to one or more of the distributed virtual computers to solve a large problem, so that the resources (e.g., memory and processing capability) of all hosts are employed in solving the problem. In other cases, the distributed virtual computers themselves can be reconfigured to perform certain computational (as contrasted with the required node tasks).
Each distributed virtual computer can be reconfigured in response to requests from either the host computer or from other nodes (distributed virtual computers) on the virtual network. Moreover, the compiling and reconfiguring of a given distributed virtual computer may be carried out either by its own FPGA(s) or by other distributed virtual computers in the virtual network or by a host.
REFERENCES:
Hastie, Neil et al.,The Implementation of Hardware Subroutines on Field Programmable Gate Arrays, Proceedings of the IEEE 1990 Custom Integrated Circuits Conference, 1990, pp. 31.4.1 to 31.4.4.*
Dillien, Paul C.,Adaptive Hardware Becomes a Reality using Electrically Reconfigurable Arrays(ERAs), IEE Colloquium on User-Configurable Logic—Technology and Applications, Dec. 1990, pp. 2/1 to 2/5.*
Dillien, Paul C., Electrically reconfigurable arrays-ERAs, IEE Colloquium on New Directions in VLSI Design, 1989, pp. 6/1 to 6/6.
Ellis Richard L.
Michaelson & Wallace
Virtual Computer Corporation
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