Viable memory cell formed using rapid thermal annealing

Details Viable memory cell formed using rapid thermal annealing Viable memory cell formed using rapid thermal annealing

1998-09-30

2001-06-26

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C438S193000, C438S195000

Reexamination Certificate

active

06251717

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to high density semiconductor devices and to a method for forming and connecting active regions and components of a high density semiconductor device, and in particular, connecting the source regions of the cells in a memory array.
BACKGROUND OF THE INVENTION
In general, memory devices such as a flash electrically erasable programmable read only memory (EEPROM) are known. For example, referring to
FIGS. 1
,
2
A, and
2
B, a flash EEPROM
100
, commonly comprises a single substrate
102
in which one or more high density core regions
104
and low density peripheral portion
106
are formed. Typical high-density cores
104
comprise at least one M×N array
104
of individually addressable, substantially identical memory cells
200
(FIGS.
2
A and
2
B). Low-density peripheral portions
106
normally include input/output (I/O) circuitry and circuitry for selectively addressing the individual cells. The selective addressing circuitry typically includes one or more x-decoders and y-decoders, cooperating with the I/O circuitry for connecting the source, the gate, and the drain of selected addressed cells to predetermined voltages or impedance to effect designated operations on the cell, e.g., programming, reading, and erasing, and deriving necessary voltages to effect such operations.
Referring now to
FIGS. 2A and 2B
, each cell
200
in core
104
includes a source
202
, a drain
204
, and channel
206
semiconductor regions formed in substrate
102
(or in an isolation well), and a stacked gate (word line) structure
210
. Gate structure
210
suitably includes a thin gate dielectric layer
212
(commonly referred to as the “tunnel oxide”) formed on the surface of substrate
102
overlying channel
206
, a floating gate
214
overlying tunnel oxide
212
, an interpoly dielectric
216
overlying floating gate
214
, and a control gate
218
overlying interpoly dielectric layer
216
. Cells
200
are arranged in a series of rows and columns.
In the completed array, the control gates
218
of the respective cells
200
in a row are formed integral to a common word line (WL) associated with the row. Columns of cells are arranged such that adjacent cells in a column share a common semiconductor region as source or drain regions. The source
202
of each cell in a column (excepting end cells) is formed in a common region with one of the adjacent cells, e.g., the preceding cell in the column. Likewise, the drain of one cell is formed in a common region with the drain
204
of the other adjacent cell, e.g., next succeeding cell in the column. The drain of each cell in a column of cells is connected by a conductive bit line (BL) (
FIG. 2B
) including an overlying layer of metal connected to each drain
204
of the cells
200
within the column. Additionally, the sources of each cell
200
in a row (and hence pairs of rows) are interconnected by a common source line CS (
FIGS. 2A
,
2
B) formed in substrate
102
, as will be described. Any particular cell
200
within array
104
can be individually addressed (programmed and read) by operating upon one word line and one bit line.
Typically, in forming an EEPROM
100
, a pattern of field oxide regions
220
is initially formed to provide electrical isolation between the respective devices of memory device
100
. For example, field oxide regions
220
are used to provide isolation between core array
104
and the devices of peripheral region
106
, as well as between the various columns of cells
200
within core array
104
. Field oxide regions are conventionally formed using a mask and selective growth process. A layer of thermal oxide (“barrier oxide” or “pad oxide”) is grown or deposited over the surface of substrate
102
. A mask, frequently composed of nitride, is deposited on the barrier oxide, and patterned to cover those regions of substrate
102
in which devices are to be formed (herein referred to as active regions). Field oxide is then grown in the exposed areas of the barrier oxide by, for example, local oxidation of silicon (LOCOS), and the masking layer and barrier oxide are stripped to expose the underlying substrate
102
. In general, referring to
FIG. 2A
, within the core
104
, the selective growth process results in alternating parallel strips of field oxide
220
and exposed regions corresponding to the columns of cells
200
in the array.
Stacked gate word line structures
210
are then typically formed. For example, tunnel dielectric
212
, suitably including a thin (e.g., approximately 100 angstroms) layer of oxide, is initially formed on substrate
102
by a suitable technique, such as, for example, thermally oxidizing the surface of substrate
102
or by depositing a suitable material on substrate
102
. A layer of suitable conductive polysilicon (e.g., polycrystalline silicon), that will ultimately form floating gates
214
, is then formed on tunnel dielectric
212
. For example, conductive polysilicon may be deposited by any suitable technique, e.g., conventional chemical vapor deposition (CVD). The polysilicon layer is typically then masked and etched to remove strips overlying field oxide regions
220
, leaving isolated strips of polysilicon on top of tunnel dielectric
212
overlying the substrate regions corresponding to the columns of cells
200
of array
104
(i.e. the regions in which source, channel, and drain regions of cells in the column will be formed). A layer of suitable dielectric material, such as, e.g., an oxide-nitride-oxide (ONO) layer, that will ultimately form interpoly dielectric
216
is typically then formed by a suitable technique. For example, where interpoly dielectric
216
is ONO, it is suitably formed by growing a layer of oxide, depositing a layer of nitride, followed by growing a layer of oxide, depositing a layer of nitride, followed by growing another layer of oxide. Interpoly dielectric layer
216
, in the completed array, insulates control gates
218
from floating gates
214
in the individual cells and electrically isolates the adjacent columns of floating gates
214
in array
104
. Another layer of suitable conductive polysilicon (e.g., polycrystalline silicon), that will ultimately form control gates
218
(and word lines WL connecting the control gates of the cells in the respective rows of array
104
) is then deposited on the interpoly dielectric layer, by a suitable technique, such as, for example, by conventional chemical vapor deposition (CVD). If desired, a silicide layer (not shown) may be provided over polysilicon layer
218
to reduce resistance. Portions of the respective polysilicon and interpoly dielectric layers are then selectively removed to define stacked gate structures
210
on tunnel dielectric layer
212
, i.e., to form the floating gates
214
, interpoly dielectric layer
216
and control gates
218
of the individual cells, and word lines WL (portions of interpoly dielectric
216
and control gate polysilicon layers, bridging field oxide regions
220
, to connect the respective cells of the rows of the array). This is typically effected by suitable masking and etching techniques. When completed, the etch creates respective generally parallel word-line structures
210
separated by a distance D
WL
, as depicted in FIG.
2
A.
Conventionally, the portions of field oxide
220
and tunnel dielectric
212
between every second pair of adjacent word lines
210
in array
104
(i.e., the regions, generally indicated as
222
, where source regions
202
are to be formed and the portions of field oxide
220
disposed between source regions
202
of the corresponding cells of adjacent columns) are then removed, in preparation for formation of the common line (CS,
FIG. 2A
) connecting the sources. This is typically effected using a conventional self-aligned source etch (SAS). As will be discussed, the selective etch, however, normally removes not only the exposed field oxide regions
220
, but also the exposed tunnel oxide
212
, a portion of the exposed polysilicon, and a portion of the underly

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