Via RC improvement for copper damascene and beyond technology

Details Via RC improvement for copper damascene and beyond technology Via RC improvement for copper damascene and beyond technology

2000-08-01

2002-02-26

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S625000, C438S626000, C438S627000, C438S629000, C438S633000, C438S637000, C438S672000, C438S675000

Reexamination Certificate

active

06350688

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing the via resistance of copper damascene interconnect plugs.
(2) Description of the Prior Art
In creating very and ultra large scale integration (VLSI and ULSI) semiconductor circuits, one of the more important aspects of this creation is the fabrication of metal interconnect lines and vias that provide the interconnection of integrated circuits in semiconductor devices. The invention specifically addresses the creation of conductive vias using the damascene process.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings also are formed. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating processing steps. The conventional dual damascene process requires two masking steps to form first the via pattern after which the pattern for the conductive lines is formed.
Using the dual damascene process, an insulating layer or a dielectric layer, such as silicon oxide, is patterned with a multiplicity of openings for conductive lines and vias. The openings are simultaneously filled with a metal, such as aluminum, and serve to interconnect the active and/or the passive elements of an integrated circuit. The dual damascene process is also used for forming multilevel conductive lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrates on which semiconductor devices are mounted. Critical to a good dual damascene structure is that the edges of the via openings in the lower half of the insulating layer are clearly defined. Furthermore, the alignment of the two masks is critical to assure that the pattern for the conductive lines aligns with the pattern of the vias. This requires a relatively large tolerance while the via may not extend over the full width of the conductive line.
FIG. 1
a
gives an overview of the steps of the damascene process, as follows:
step 01 shows the formation of the metal plug,
step 02 shows the deposition of the Intra-Level Dielectric (ILD),
step 03 shows the formation of the trenches for metal lines,
step 04 shows the deposition of metal to fill the trenches, and
step 05 shows the removal of metal from the surface.
The damascene process is further explained below, the numbers indicated within this explanation refer to the cross section of a damascene structure that is shown in
FIG. 1
b.
Referring now specifically to
FIG. 1
a,
step 01, there is shown the formation of a metal via plug
10
in the surface of a semiconductor substrate
14
(
FIG. 1
b
). Any micro-scratch in the surface of the substrate
14
will fill with metal during subsequent metal deposition and can cause electrical shorts between adjacent via plugs
10
or between electrical lines deposited on top of surface
12
. To remove the damascene residue and to remove the scratch count on the surface
12
, surface
12
is polished and buffed after the metal plug
10
has been created.
FIG. 1
a,
step 02 shows the deposition of the Intra-Level Dielectric (ILD)
16
(
FIG. 1
b
) which can be deposited using Plasma Enhanced CVD (PECVD) technology. Dielectric
16
can, for instance, be SiO
2
.
FIG. 1
a,
step 03 shows the formation of the trenches
22
(
FIG. 1
b
) for the metal lines, these trenches
22
can be formed using Reactive Ion Etching (RIE) technology.
FIG. 1
a,
step 04 shows the deposition of metal to fill the trenches
22
, this process can use either the CVD or a metal flow process. The excess metal on the surface
26
is removed using the CMP process, see
FIG. 1
a,
step 05, and a planar structure
26
with metal inlays
22
in the intra-level dielectric
16
is achieved.
For many of the applications of the damascene process, a thin barrier layer is deposited over the inside of the opening for the damascene conducting line (thereby covering the bottom and the sidewalls of this opening) prior to the formation of the damascene conducting line. Frequently used material for this barrier layer is TaN/Ta. This layer of TaN/Ta prevents diffusion of the copper of conducting line into the surrounding dielectric during the formation of the copper conducting line. The barrier layer typically has a thickness of about 300 Angstrom.
In addition, a copper seed layer can be deposited over the surface of the barrier layer, this seed copper facilitates and enhances the formation of the copper conducting line during its deposition. A copper seed layer typically has a thickness of about 1600 Angstrom.
The damascene process, as already indicated above, first etches the conductor pattern into the dielectric after which the etched pattern is filled with metal to create the buried metalization that also has a surface of good planarity. This damascene process also eliminates the need of a dielectric deposition in order to fill the gaps. A planarized metal deposition process can be used for this to fill the pattern that has been created in a dielectric layer of SiO
2
. An etchback or CMP process will remove the excess metal over the field regions. CMP thereby offers the advantage of providing a globally planarized surface. The indicated processing steps can be applied to both single and dual damascene.
For the dual damascene process, the processing steps can follow three approaches. The dual damascene structure consists of a lower (via plug) part and an upper (interconnect line) part.
Approach 1, the via is created first. This approach uses a double layer stack of dielectric whereby the layers of dielectric are separated by an etch stop layer typically containing SiN. A lowest etch stop layer is deposited over the surface of the substrate on which the dual damascene structure is to be created, this lowest etch stop layer is the etch stop for the via etch. The vias are formed by resist patterning after which an etch through the double layer dielectric stack is performed. This is followed by patterning the conductor (interconnect line) in the top layer of SiO
2
thereby using the inter-dielectric etch stop layer of SiN as the etch stop layer.
Approach 2, the conductor first process. The conductor patterns is formed by resist patterning and by etching the conductor patterns into the upper SiO
2
layer thereby using the SiN layer as an etch stop layer. This is followed by via resist patterning and etching through the thin layer of SiN and the lower SiO
2
layer.
Approach 3, the etch stop layer first. The first SiO
2
layer is deposited, followed by the thin layer of SiN as etch stop, followed by the via resist patterning and etching of the SiN layer. This is followed by depositing the top SiO
2
layer and then the conductor patterning. In etching the conductor pattern in the top SiO
2
layer, the etching process will be stopped by the SiN layer except where the via holes are already opened in the SiN layer thereby completing the via holes etching in the first SiO
2
layer simultaneously.
The creation of a dual damascene structure is highlighted by an example as shown in
FIGS. 2
a
and
2
b.
FIG. 2
a
gives and overview of the sequence of steps required of forming a Prior Art dual damascene structure. The numbers referred to in the following description of the formation of the dual damascene structure relate to the cross section of the completed dual damascene structure that is shown in
FIG. 2
b.
FIG. 2
a
gives an overview of the sequence of steps required for forming a Prior Art dual damascene structure. The numbers referred to in the following description of the formation of the dual damascene structure relate to the cross section of the completed dual damascene structure that is shown in
FIG. 2
b.
FIG. 2
a,
52
shows the deposition with

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