Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1997-12-01
2001-04-10
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S797000, C257S758000, C438S014000
Reexamination Certificate
active
06215129
ABSTRACT:
TECHNICAL FIELD
The present claimed invention relates to the field of semiconductor devices. More specifically, the present claimed invention relates to the manufacturing of semiconductor devices.
BACKGROUND ART
As semiconductor processing and fabrication techniques improve, the size of various semiconductor features is reduced. This reduction in size, in turn, allows for the advantageous placement of a greater number of semiconductor devices in a given area. Unfortunately, such reduction in the size of various semiconductor features is not without drawbacks.
One example of a drawback associated with the reduction in size of semiconductor features is found in the area of via inspection. Specifically, as the critical dimension (i.e. the diameter as measured at the bottom of the via) becomes smaller than approximately 0.6 microns, conventional optical inspection is not a feasible method for measuring the critical dimension of the via. Thus, when the critical dimension of a via is less than approximately 0.6 microns a scanning electron microscope examination of the via is required.
With reference now to Prior Art
FIG. 1
, a side sectional view of a dielectric material
100
having a via
102
formed therein is shown. During a scanning electron microscope examination of via
102
, secondary electrons (typically represented by arrows
104
and
106
are generated. Unfortunately, during conventional via examination processes, such secondary electrons
104
and
106
are often absorbed by the material through which the via is formed. As a result, detector
108
does not receive (i.e. detect) secondary electrons
104
and
106
. Thus, a conventional scanning electron microscope examination of the via does not always provide an accurate measurement of the via's critical dimension.
As yet another drawback, conventional via examination processes (e.g. optical inspection and scanning electron microscope examination) do not readily provide information on various other parameters of the via being examined. For example, conventional scanning electron microscope examination processes do not readily indicate the depth to which the via has been etched into an underlying material. As a result, in conventional via examination processes, it is not easy to determine if a via extends deep enough into the underlying material. That is, it is difficult to determine if the via “cleared” the depth necessary to ensure that the via opens to the underlying conductive layer. Most commonly, this information is not available until the device is completed and passes electrical tests.
As still another drawback associated with conventional via inspection methods, such prior art approaches do not provide information on the alignment/registration of the via mask. That is, conventional approaches do not readily provide information on the difference between the actual location of a via and the intended location of the via. Therefore, conventional methods require a separate and distinct measurement process to determine the degree of misalignment present in the formation of the vias, or more commonly, the information is not obtained at all.
Thus, a need exists for an apparatus and method for measuring the critical dimension of a via wherein the apparatus and method is feasible even for a via having a critical dimension of less than approximately 0.6 microns. A further need exists for a via formation apparatus and method which readily indicates whether a via has been formed to a desired depth into the underlying dielectric material. Still a further need exists for an apparatus and method which determines the degree of misalignment present in the formation via patterning process.
DISCLOSURE OF THE INVENTION
The present invention provides an apparatus and method for measuring the critical dimension of a via wherein the apparatus and method is feasible even for a via having a critical dimension of less than approximately 0.6 microns. The present invention also provides a via formation apparatus and method which readily indicates whether a via has been formed to a desired depth into the underlying dielectric material. The present invention further provides an apparatus and method which determines the degree of misalignment present in the formation of a via.
Specifically, in one embodiment, the present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to repel secondary electrons which are generated during a scanning electron microscope examination of the vias. This facilitates SEM imaging of the bottom of the via hole. In the present embodiment, the sample structure is disposed within the material through which the plurality of vias are to be formed such that the top surface of the conductive, but electrically isolated (floating ground) sample structure is disposed at a depth which is at least as great as the intended depth of the plurality of vias. Additionally, in the present embodiment, the plurality of vias to be formed are disposed intentionally offset with respect to the sample conductive structure. As a result, the secondary electrons, which are imaged from the conductive surface at the bottom of the via hole, characterize the degree of misalignment present in the via formation process. In so doing, the present invention provides information regarding the critical dimension of the vias (diameter) and the alignment/registration of the via formation process, and determines whether or not the vias are etched to a desired depth, all at the same time.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
REFERENCES:
patent: 4642672 (1987-02-01), Kitakata
patent: 5457334 (1995-10-01), Nishimoto
patent: 5736863 (1998-04-01), Liu
patent: 5780870 (1998-07-01), Maeda et al.
patent: 5847466 (1998-12-01), Ito et al.
patent: 5856705 (1999-01-01), Ting
patent: 5869877 (1999-02-01), Patrick et al.
patent: 5900672 (1999-05-01), Chan et al.
Harvey Ian Robert
Sethi Satyendra
Lee Eddie C.
VSLI Technology, Inc.
Wagner , Murabito & Hao LLP
Wilson Allan R.
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