Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-23
2001-01-30
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000, C438S592000
Reexamination Certificate
active
06180468
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the implantation of channels in semiconductors and more particularly to the reduction of the process thermal budget for channel implantation.
BACKGROUND ART
In the manufacture of semiconductors, a silicon substrate is subject to a large number of processes before the final semiconductor devices are completed. In making transistors, there are a number of steps starting from implanting various dopants into the semiconductor substrate, depositing insulating gate oxides, forming gates, and implanting various doping elements to form the source/drain junctions (and source/drain extension junctions for more recent sub-0.25 micron transistors). Each of the implantation steps often require a thermal anneal, or heating step, to activate, or cause to become electrically active, of the implanted material. Generally, the thermal anneal requires a certain amount of time, and the temperature times the time for a particular step is called the step thermal budget. The total thermal budget for all the steps in the manufacturing process is called the process thermal budget.
As semiconductors are reduced in size, a major problem occurs in that the source/drain junctions and their extensions become so close that the electrons punch-through effect occurs so leakage current flows between them. It is to prevent this problem that dopants are added to the channel. The difficulty is that the dopant is usually added at the beginning of the process and then is subject to additional cycles of thermal anneal as additional implantation and diffusion steps are implemented as explained above. The thermal budget is essentially the temperature multiplied by time that a region is subjected to. A long duration, high temperature step requires a high thermal budget. The lighter doping near the channel surface of the silicon is desirable to increase carrier mobility and reduce scattering while the higher doping in the channel subsurface is desirable to eliminate the punch-through effect. The ideal situation is to have all the processing done at as low a temperature as possible for as short a period as possible to prevent massive diffusion. But enough thermal budget is required to activate the dopant.
The reduction of process thermal budget is very critical in fabricating sub-100 nm MOS transistors. In order to suppress the so-called “short-channel effect” which degrades transistor performance and manufacturability, ultra-low thermal budget processes for channel dopant implant are required. Further, a large thermal budget also causes the doping in the channel to diffuse towards the source/drain junction, which increases the parasitic capacitance. This, in turn, degrades the MOS field-effect transistor speed.
In an ideal process, the dopant concentration near the silicon surface should be very low because it is beneficial to the carrier mobility. At the same time, the dopant concentration in the subsurface of the silicon should be very high before dropping off, because it provides good immunity to short-channel effect (such as threshold voltage roll-off, drain-induced-barrier lowering, and source/drain punch-through, etc.)
The difference in the dopant concentration is usually 1 to 2 orders of magnitude. However, achieving a sharp transition in the doping profile is extremely difficult in a CMOS process. One of the major reasons is that in a conventional CMOS process, the channel implant must be performed before the source/drain implant anneal and the source/drain extension implant anneal. Therefore, the total thermal budget for the channel implant is large because it includes the thermal budgets for the source/drain implant and the source/drain extension implant. Thus, any initial, sharp doping profile is diffused by the additional thermal input.
Thus, as transistors have shrunk in size, there has been an intense search for the ideal process by which the dopant concentration near the silicon surface can be very low while the concentration in the subsurface is very high. This has been very difficult, if not impossible, to achieve previously.
DISCLOSURE OF THE INVENTION
The present invention provides an ultra-low thermal budget process for channel implant by using a reverse process sequence where a conventional MOS transistor is formed without the channel implant. The originally deposited polysilicon gate material is removed, a nitride film deposition and etch is used to form a configured nitride spacer defining an implant opening, and a self-aligned channel implant is performed. After the super-retrograded channel implantation, the nitride spacer and the original gate oxide are removed for subsequent regrowth of a second gate oxide and a polysilicon deposition to reform the polysilicon gate. The anneal of the channel implant is performed after the anneals for source/drain junctions and source/drain extension junctions.
The present invention provides a very low thermal budget for the retrograded channel doping implant because the channel implant is performed after the source/drain implant, the source/drain extension implants, and the corresponding thermal annealing processes.
The present invention further provides a channel implant with a very sharp doping profile.
The present invention still further provides a channel implant which is self-aligned to the polysilicon gate.
The present invention still further provides a controlled, spatially-confined implant which can be spaced away from the source/drain junction to avoid increasing the parasitic junction capacitance.
The present invention still further provides for a regrown gate oxide and redeposited gate without the plasma etching steps in a conventional gate stack formation. This helps avoid the plasma-induced thin gate oxide damage which causes device reliability problems.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5168072 (1992-12-01), Moslehi
patent: 5545579 (1996-08-01), Laing et al.
patent: 5576227 (1996-11-01), Hsu
patent: 5767557 (1998-06-01), Kizilyali
patent: 5856225 (1999-01-01), Lee et al.
patent: 5858843 (1999-01-01), Doyle et al.
patent: 5904530 (1999-05-01), Shin
patent: 5917219 (1999-06-01), Nandakumar
patent: 5952693 (1999-09-01), Wu et al.
Ishida Emi
Luning Scott
Thurgate Timothy
Yu Bin
Advanced Micro Devices , Inc.
Elms Richard
Ishimaru Mikio
Lebentritt Michael S.
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