Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-01-24
2004-08-10
Thai, Luan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S778000, C257S779000, C257S780000, C257S723000, C257S724000, C257S738000
Reexamination Certificate
active
06774475
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory structures and more particularly to an improved vertically stacked memory structure.
2. Description of the Related Art
With each new generation of electronic and computing devices, the size of the devices decreases while their operating speed increases. An important feature within such devices is the ability to store information using, for example, dynamic random access memory (DRAM) arrays.
The size of the memory arrays can be reduced by reducing the size of the individual memory devices and/or packing the memory devices closer together. In addition, the arrays can be stacked vertically so that additional memory arrays can be utilized without increasing the overall “footprint.” Data in memory devices is addressed by calling out a particular coordinate in a rectangular array. Memory configurations may be described in such terms as 256K by 4. In this case, there are 4 memory arrays consisting of approximately 256,000 distinct data locations each. In memory addressing, in this case, there will be one set of address pins per module, sufficient to identify a single element of a binary array of 256,000 elements. When reading and writing data, 4 bits of data from identical locations in each array are read or written using the same address setup. Address pins are shared by 4 array elements, limiting needed address pins and their interconnects to ¼ the number needed if each array were addressed separately. In single module stacked memories, addresses are commoned between modules in the stack, but each stack requires a full complement of address interconnects. One such stacked memory array is shown in U.S. Pat. No. 6,268,649, to Corisis et al. (hereinafter “Corisis”), the disclosure of which is incorporated herein by reference for the purpose of indicating the background of the present invention.
In the Corisis patent, a stackable fine ball grid array (FBGA) package is disclosed that allows the stacking of one array upon another. This stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of a semiconductor device (integrated circuit (IC) device) mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device. Wire interconnects connect the IC device in a way that does not increase the overall profile of the package. Encapsulating material protects both the IC device and the wire interconnect as the conductive elements make contact with the FBGA, positioned below or above, to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA.
Certain pins on the FBGA in the stack may require an isolated connection to the PC board. This allows IC devices to be stacked one upon the other while maintaining a unique pin out for each pin required in the stack. The number of chips commonly addressed in the stack is expanded to an optimum extent such that the number of memory address interconnects in the stacked module assembly is minimized. In this optimum structure, the number of data bits addressed in parallel is equal to the system word width. With such a structure, for each chip added to a deck in the stack structure, an address complement of interconnects needed to expand in the height direction is eliminated.
In some conventional structures, there is a single memory chip per vertical deck of the stack. This permits the assembly to expand in the height dimension only. If two or more chips are included per vertical deck of the stack, a yield detractor arises. Memory chips must be “burned in” to reduce infant mortality in order to produce acceptable field reliability performance. Conventional socket technology requires that chips be packaged in a first level package, such as an individual deck, for practical burn in. Expanding such conventional methods of using more than one chip per stack deck requires that the burn in be done at the deck level, resulting in the discard of one or more good memory chips for each infant mortality failure of a chip in that deck's burn in. Increasing the number of chips per deck increases the risk that a defective chip will be included in the deck. With the wire bonded structure used to bond chips to decks, it is difficult or impossible to remove a single defective chip. Therefore, if a defective chip is included on a deck, the entire deck must be discarded, often resulting in the discard of a large number of non-defective chips. If the structure is expanded to include multiple devices per deck, it becomes expensive and time-consuming to manufacture (especially when the “burn-in” and testing procedures are completed) and has a low yield (high defect) rate. For this reason, conventional structures must use significantly more than the optimum (minimum) number of solder interconnects to address a given memory structure.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional stacked memory structures, the present invention has been devised, and it is an object of the present invention, to provide a structure and method for an improved stacked memory structure that has a low defect rate.
In order to attain the object suggested above, there is provided, according to one aspect of the invention, a memory structure including a plurality of substrates stacked one on another. The invention includes connectors that connect the substrates to one another and memory chip packages mounted on each of the substrates. The connectors have a size sufficient to form a gap between the substrates. The gap is larger than a height of the memory chip packages.
Each of the memory chip packages has a pre-tested memory chip package that is tested for defects before being mounted on the substrates. The memory chip packages and the substrates include identical electrical connections. Each of the substrates has a plurality of the memory chip packages mounted thereon. The connectors include solder balls. The invention also has a thermal connection between a top of the memory chip packages and a bottom of an adjacent substrate such that the thermal connection fills the gap. The memory chip packages each include an array of memory elements mounted within a package.
REFERENCES:
patent: 5655290 (1997-08-01), Moresco et al.
patent: 5694366 (1997-12-01), Chevallier et al.
patent: 5783870 (1998-07-01), Mostafazadeh et al.
patent: 5854507 (1998-12-01), Miremadi et al.
patent: 5907903 (1999-06-01), Ameen et al.
patent: 6051878 (2000-04-01), Akram et al.
patent: 6072233 (2000-06-01), Corisis et al.
patent: 6268649 (2001-07-01), Corisis et al.
patent: 2002/0086459 (2002-07-01), Nakajima
Beausoleil William F.
Blackshear Edmund D.
Tomassetti N. James
Anderson, Esq. Jay H.
McGinn & Gibb PLLC
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