Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-09-11
2000-01-04
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438271, 438712, 438713, 438728, 438978, 438695, H01L 218234, H01L 218244
Patent
active
060109300
ABSTRACT:
Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier. The etch is subsequently performed with the use of a diatomic chlorine etchant. Four embodiments are disclosed as variations on the step of etching the polysilicon with the diatomic chlorine etch chemistry.
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Brown Kris K.
Keller David J.
Liu Louie
Hack Jonathan
Micro)n Technology, Inc.
Niebling John F.
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