Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-28
2001-05-29
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C361S760000, C361S767000, C361S768000, C361S772000, C361S773000
Reexamination Certificate
active
06239012
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to chip-on-board assemblies. Particularly, the present invention relates to vertically mountable, bare or minimally packaged semiconductor devices. The semiconductor devices to which the present invention relates include bond pads proximate an edge thereof. In use, the solder bump establishes an electrical connection with a terminal of a carrier substrate, and supports the semiconductor device perpendicularly relative to the carrier substrate.
2. Background of Related Art
The direct attachment of a semiconductor device to a circuit board is known in the art as chip-on-board technology. Semiconductor devices that are directly mountable to a circuit board typically include bond pads along more than one edge thereof or in an area array over the active surface thereof. Methods for attaching semiconductor devices directly to a circuit board include flip-chip technology and tape automated bonding. Typically, when those techniques are employed, a semiconductor device is oriented over the circuit board and substantially parallel thereto in order to establish an electrical connection between the semiconductor device and the circuit board. After connecting such a semiconductor device to a circuit board, a protective coating may be applied over the semiconductor device.
However, the placement of a semiconductor device directly against a circuit board is somewhat undesirable in that, due to the parallel orientation of the semiconductor device relative to the circuit board and the typical placement of the semiconductor device's active surface thereagainst, heat must pass through both the circuit board and the semiconductor device in order to dissipate from the semiconductor device. Thus, the transfer of heat away from the semiconductor device is relatively slow. The horizontal orientation of the semiconductor device also consumes a great deal of “real estate” or area on the circuit board.
Vertical surface mount packages are also known in the art. When compared with traditional, horizontally mountable semiconductor packages and chip-on-board semiconductor devices, many vertical surface mount packages have a superior ability to transfer heat away from the semiconductor device. Vertical surface mount packages also consume less area on a circuit board than a horizontally mounted package of the same size. Thus, many skilled individuals in the semiconductor industry are finding vertical surface mount packages more desirable than their traditional, horizontally mountable counterparts and horizontally mountable chip-on-board devices.
The following United States patents disclose various exemplary vertical surface mount packages: U.S. Pat. No. Re. 34,794, issued to Warren M. Farnworth on Nov. 22, 1994; U.S. Pat. No. 5,444,304, issued to Kouija Hara and Jun Tanabe on Aug. 22, 1995; U.S. Pat. No. 5,450,289, issued to Yooung D. Kweon and Min C. An on Sep. 12, 1995; U.S. Pat. No. 5,451,815, issued to Norio Taniguchi et al. on Sep. 19, 1995; U.S. Pat. No. 5,592,019, issued to Tetsuya Ueda et al. on Jan. 7, 1997; and U.S. Pat. No. 5,635,760, issued to Toru Ishikawa on Jun. 3, 1997.
Many vertical surface mount packages in the prior art are somewhat undesirable in that they include leads which operatively connect a semiconductor device to a circuit board. The leads of such devices tend to increase the impedance and decrease the overall speed with which a device conducts electrical signals. Moreover, the packaging of many such devices adds to their undesirability. Typically, packaging requires multiple additional manufacturing steps, which translates into increased production costs. The packaging of many vertical surface mount packages also tends to consume a substantial amount of space on the circuit board.
U.S. Pat. No. 5,668,409 (the “'409 patent”), issued to Stephen Joseph Gaul on Sep. 16, 1997, discloses a vertically mountable, bare semiconductor die which includes bond pads along the edge thereof. The '409 patent discloses vertical mounting of that device to a circuit board by solder reflow techniques. However, that device is somewhat undesirable in that fabrication thereof requires several additional steps relative to the fabrication of typical chip-on-board semiconductor devices. The requirement of additional fabrication steps and the related requirement of additional fabrication materials increases the manufacturing cost of such semiconductor devices.
Thus, a vertically mountable bare semiconductor device is needed which has reduced impedance relative to devices in the prior art, has good thermal conductivity, and consumes less space on a circuit board. A method of mounting a bare or minimally packaged semiconductor device perpendicularly relative to a circuit board is also needed.
SUMMARY OF THE INVENTION
The semiconductor device of the present invention includes bond pads disposed proximate a single edge thereof. Placement of the bond pads proximate an edge of the semiconductor device facilitates direct vertical mounting of the semiconductor device to a carrier substrate. Thus, when such a semiconductor device is substantially perpendicularly mounted to a carrier substrate, packaging and leads are not necessary to establish an electrical connection between the bond pads and the corresponding terminals on the carrier substrate. The direct connection between the bond pads and substrate board contacts also imparts to the semiconductor device assembly of the present invention a low impedance characteristic.
A preferred mounting method according to the present invention includes the placement of a brick of solder paste on the carrier substrate terminals, orienting the semiconductor device perpendicularly relative to the carrier substrate, aligning the bond pads of the semiconductor device with their corresponding terminals, establishing contact between the bumps and the solder paste, and heating the bumps and solder paste to reflow the solder and attach the bond pads to their respective terminals.
Other advantages of the present invention will become apparent through a consideration of the appended drawings and the ensuing description.
REFERENCES:
patent: Re. 34794 (1994-11-01), Farnworth
patent: 3624587 (1971-11-01), Conrad
patent: 5444294 (1995-08-01), Suzuki
patent: 5444304 (1995-08-01), Hara et al.
patent: 5450289 (1995-09-01), Kweon et al.
patent: 5451815 (1995-09-01), Taniguchi et al.
patent: 5468991 (1995-11-01), Lee et al.
patent: 5592019 (1997-01-01), Ueda et al.
patent: 5619067 (1997-04-01), Sua et al.
patent: 5635760 (1997-06-01), Ishikawa
patent: 5668409 (1997-09-01), Gaul
patent: 5889658 (1999-03-01), Sullivan et al.
patent: 5940277 (1999-08-01), Farnworth et al.
Micro)n Technology, Inc.
Niebling John F.
Trask & Britt
Zarneke David A
LandOfFree
Vertically mountable semiconductor device and methods does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertically mountable semiconductor device and methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertically mountable semiconductor device and methods will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2447019