Vertical transistor interconnect structure and fabrication metho

Details Vertical transistor interconnect structure and fabrication metho Vertical transistor interconnect structure and fabrication metho

1997-03-04

1999-08-03

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438275, 438589, H01L 218238

Patent

active

059337176

ABSTRACT:
It has been discovered that improvements in the compactness and performance of integrated circuit devices are gained through the fabrication of vertical transistors for which channel sizes are determined by the accuracy of etch techniques rather than the resolution of photolithographic techniques. Etching in the vertical dimension is precisely controlled to resolutions of about 0.1 .mu.m while advanced photolithographic techniques in a volume production environment achieve resolutions of 0.25 .mu.m. Interconnect structures for connecting to high density vertical transistors are formed by depositing metal into the trenches etched during fabrication of the vertical transistors. A method of fabricating an integrated circuit includes etching a trench with a sidewall in a substrate wafer and forming a vertical transistor on the sidewall. The vertical transistor has a drain, a channel and a source doped at a series of vertical depths in the substrate wafer. The transistor has a gate coupled to the sidewall adjacent to the drain, the channel, and the source. The method of fabricating an integrated circuit further includes forming an interconnect in the trench coupled to the vertical transistor. An integrated circuit includes a substrate wafer having a trench with a sidewall and a vertical transistor formed on the sidewall of the trench. The vertical transistor has a drain, a channel and a source doped at a series of vertical depths in the substrate wafer. The vertical transistor has a gate coupled to the sidewall adjacent to the drain, the channel, and the source. The integrated circuit further includes an interconnect in the trench coupled to the vertical transistor.

REFERENCES:
patent: 4589193 (1986-05-01), Goth et al.
patent: 4717682 (1988-01-01), Taka et al.
patent: 4916083 (1990-04-01), Monkowski et al.
patent: 5032882 (1991-07-01), Okumura et al.
patent: 5077228 (1991-12-01), Eklund et al.
patent: 5164325 (1992-11-01), Cogan et al.
patent: 5242845 (1993-09-01), Baba et al.
patent: 5250450 (1993-10-01), Lee et al.
patent: 5358884 (1994-10-01), Voilette
patent: 5429977 (1995-07-01), Lu et al.
patent: 5464780 (1995-11-01), Yamazaki
patent: 5705409 (1998-01-01), Witek
patent: 5719067 (1998-02-01), Gardner et al.
patent: 5721148 (1998-02-01), Nishimura
patent: 5726088 (1998-03-01), Yanagiya etal.
patent: 5770514 (1998-06-01), Matsuda et al.
patent: 5773343 (1998-06-01), Lee et al.

Affiliated with

Also associated with

Rating

Vertical transistor interconnect structure and fabrication metho does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vertical transistor interconnect structure and fabrication metho, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical transistor interconnect structure and fabrication metho will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-859550