Vertical transistor and memory cell

Details Vertical transistor and memory cell Vertical transistor and memory cell

1997-09-08

2000-01-25

Thomas, T.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257329, 257 71, H01L 27108, H01L 2976

Patent

active

060181761

ABSTRACT:
A method for manufacturing a three-dimensionally structured vertical transistor or memory cell forms a silicon-on-insulator (SOI) structure on a semiconductor substrate and sequentially deposits a drain region, a channel region and a source region on the SOI substrate structure. The transistor includes a cylinder-type gate insulation layer surrounding the channel region and a gate electrode surrounding the gate insulation layer, having increased integration. This process and structure avoid the characteristic degradation caused by the leakage current associated with the trench process and structure.

REFERENCES:
patent: 5561308 (1996-10-01), Kamata et al.

Affiliated with

Also associated with

Rating

Vertical transistor and memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vertical transistor and memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical transistor and memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2317655