Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2006-02-07
2006-02-07
Abraham, Fetsum (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S329000, C438S149000
Reexamination Certificate
active
06995053
ABSTRACT:
A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a substrate insulation layer; forming a gate oxide layer overlying the gate sidewalls, and a gate insulation layer overlying the gate top surface; etching the exposed substrate insulation layer; forming a first source/drain region overlying the gate insulation layer; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall with a channel length about equal to the thickness of the gate, interposed between the first and second source/drain regions.
REFERENCES:
patent: 5032529 (1991-07-01), Beitman et al.
patent: 6566714 (2003-05-01), Deane et al.
patent: 6881994 (2005-04-01), Lee et al.
patent: 2004/0202032 (2004-10-01), Forbes
Schuele Paul J.
Voutsas Apostolos T.
Abraham Fetsum
Ripma David C.
Sharp Laboratories of America Inc.
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