Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-27
2004-12-07
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S595000, C438S696000, C438S703000, C438S713000, C438S778000
Reexamination Certificate
active
06828186
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to spacer layers formed within microelectronic products. More particularly, the present invention relates to vertical sidewall profile spacer layers formed within microelectronic products.
2. Description of the Related Art
The use of spacer layers is common in the microelectronic product fabrication art for spacing microelectronic structures within microelectronic products. A particularly common use of a spacer layer is for spacing a gate electrode from a heavily doped portion of a source/drain region within a field effect transistor (FET) device employed within a semiconductor product.
Spacer. layers are desirable and often essential in the microelectronic product fabrication art. However, spacer layers are nonetheless not entirely without problems.
In that regard, spacer layers are often difficult to form with enhanced spacer layer profiles. For example, substantially vertical spacer layer sidewall profiles are often desirable since they generally provide a more precise spacing of separated structures within microelectronic products.
It is thus desirable to form spacer layers with enhanced profiles.
It is towards the foregoing object that the present invention is directed.
Various spacer layers having desirable properties, and methods for fabrication thereof, have been disclosed in the microelectronic product fabrication art.
Included but not limiting are spacer layers and methods disclosed within Wieczorek et al., in U.S. Pat. No. 6,121,138 (a silicon nitride spacer layer having a substantially vertical sidewall profile such as to attenuate salicide bridging between a gate electrode and source/drain region separated by the spacer layer within a FET device).
The teachings of the foregoing reference are incorporated herein fully by reference.
Desirable for use within microelectronic products are additional spacer layers with enhanced profiles, and methods for fabrication thereof.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the invention is to provide a spacer layer for use within a microelectronic product, and a method for fabrication thereof.
A second object of the invention is to provide a spacer layer and method in accord with the first object of the invention, wherein the spacer layer is formed with enhanced profile.
In accord with the foregoing objects, the present invention provides: (1) a method for fabricating a spacer layer within a microelectronic product; and (2) a microelectronic product having formed therein a spacer layer.
The method first provides a substrate having formed thereover a topographic feature having a substantially vertical first sidewall. The method next provides for forming over the substrate, including the topographic feature, a blanket spacer material layer having a reentrant sidewall profile with respect to the substantially vertical first sidewall. Finally, the method provides for anisotropically etching the blanket spacer material layer to form a spacer layer adjoining the substantially vertical first sidewall of the topographic feature. Within the method, the spacer layer has a second sidewall at least in part substantially vertical and laterally separated from the substantially vertical first sidewall of the topographic feature.
The method of the invention contemplates the microelectronic product having formed therein the spacer-layer in accord with the method of the invention.
Within the invention, the blanket spacer material layer having the reentrant sidewall profile with respect to the topographic feature may be formed as a laminate of a blanket conformal first spacer material layer and a blanket reentrant second spacer material layer.
The invention provides a spacer layer for use within a microelectronic product, and a method for fabrication thereof, wherein the spacer layer is formed with enhanced profile.
The present invention realizes the foregoing object by employing a blanket spacer material layer having a reentrant sidewall profile with respect to a topographic feature having a substantially vertical first sidewall profile. Upon anisotropic etching, the blanket spacer material layer yields a spacer layer having at least in part a substantially vertical second sidewall profile laterally separated from the substantially vertical first sidewall profile.
REFERENCES:
patent: 5736446 (1998-04-01), Wu
patent: 5760435 (1998-06-01), Pan
patent: 5786256 (1998-07-01), Gardner et al.
patent: 6121138 (2000-09-01), Wieczorek et al.
patent: 6207532 (2001-03-01), Lin et al.
patent: 2003/0211697 (2003-11-01), Hsu et al.
Liu Shih-Chiang
Lo Chi-Hsin
Tsai Chia-Shiang
Fourson George
Garcia Joannie Adelle
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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