Vertical semiconductor devices

Details Vertical semiconductor devices Vertical semiconductor devices

2005-05-03

2005-05-03

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S242000, C438S246000, C257S301000, C257S302000

Reexamination Certificate

active

06887761

ABSTRACT:
A method and structure for increasing the threshold voltage of vertical semiconductor devices. The method comprises creating a deep trench in a substrate whose semiconductor material has an orientation plane perpendicular to the surface of the substrate. Then, vertical transistors are formed around and along the depth of the deep trench. Next, two shallow trench isolation are formed such that they sandwich the deep trench in an active region and the two shallow trench isolation regions abut the active region via planes perpendicular to the orientation plane. Then, the channel regions of the vertical transistors are exposed to the atmosphere in the deep trench and then chemically etched to planes parallel to the orientation plane. Then, a gate dielectric layer is formed on the wall of the deep trench. Finally, the deep trench is filled with poly-silicon to form the gate for the vertical transistors.

REFERENCES:
patent: 5937292 (1999-08-01), Hammerl et al.
patent: 6090661 (2000-07-01), Perng et al.
patent: 6100131 (2000-08-01), Alsmeier
patent: 6326261 (2001-12-01), Tsang et al.
patent: 6362040 (2002-03-01), Tews et al.
patent: 6518616 (2003-02-01), Dyer et al.
patent: 6794242 (2004-09-01), Dyer et al.

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